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Superconductor Science and Technology

Design and fabrication of integrator using adiabatic quantum-flux-parametron circuit

Hongxiang Shen, Zeyu Han, Zongyuan Li, Yuxing He, Nobuyuki Yoshikawa

Published Jan 19, 2025• 0 citations
Publisher

Abstract

Abstract We believe that the adiabatic quantum flux parametron (AQFP) circuit, as a novel low-power superconducting circuit technology, has potential application in various fields, including utilizing its high precision to determine the phase of input signals. To improve the precision of AQFP circuits, it is crucial to reduce the gray zone of the system. In this paper, we investigate a digital integration method to reduce the gray zone and enhance the precision of the AQFP circuits. Theoretical analysis demonstrates that the gray zone narrows, and the precision of the system improves as more data points are integrated. Additionally, we establish the quantitative relationship between the reduction in gray zone and the number of integrated data points. To validate these findings, we fabricate AQFP integrator circuits and perform experimental verification. Furthermore, we estimate the relationship between the scale of the integration circuit and the chip area, emphasizing possibilities for various future application scenarios.

DOI
10.1088/1361-6668/adabcb

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Abstract We believe that the adiabatic quantum flux parametron (AQFP) circuit, as a novel low-power superconducting circuit technology, has potential application in various fields, including utilizing its high precision to determine the phase of input signals. To improve the precision of AQFP circuits, it is crucial to reduce the gray zone of the system. In this paper, we investigate a digital integration method to reduce the gray zone and enhance the precision of the AQFP circuits. Theoretical analysis demonstrates that the gray zone narrows, and the precision of the system improves as more data points are integrated. Additionally, we establish the quantitative relationship between the reduction in gray zone and the number of integrated data points. To validate these findings, we fabricate AQFP integrator circuits and perform experimental verification. Furthermore, we estimate the relationship between the scale of the integration circuit and the chip area, emphasizing possibilities for various future application scenarios.
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An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.
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Abstract The adiabatic quantum-flux-parametron (AQFP), which can operate with ultra-low energy consumption, has attracted attention as an alternative to semiconductor circuits. The development of reconfigurable AQFP devices is essential for advancing AQFP integrated circuits. However, research on reconfigurable devices at the logic gate level remains limited. We propose an AQFP circuit capable of reconfiguring its logic function by controlling the superconducting phase shift through externally applied magnetic flux. In AQFP logic, logic ‘1’ and ‘0’ are represented by the polarity of the current. The proposed circuit can switch between the Buffer function, which propagates the input current with its polarity unchanged, and the NOT function, which propagates it with the polarity inverted. We analytically derived the parameter conditions for correct operation and determined the parameters within this range to achieve adiabatic operation and sufficient element margins for experimental demonstration. We fabricated the proposed reconfigurable circuit using the 10 kA cm −2 Nb four-layer superconducting circuit fabrication process, and experimentally confirmed correct operation for both the Buffer and NOT functions. The control current margins, which are responsible for the functional reconfiguration, were −2.3% to +31.2% for chip 1 and +0.8% to +35.1% for chip 2. Both margins had widths comparable to the simulation result. This work presents the first experimental demonstration of an AQFP circuit whose function can be reconfigured using only a control current. We believe this work will contribute to the advancement of reconfigurable AQFP devices.
Abstract We report on the design and implementation of adiabatic quantum flux parametron (AQFP) buffer gates utilizing cross-type Nb/AlO x /Nb Josephson junctions with I C of 20 μ A, designed to operate at mK temperatures. We, therefore, discuss design considerations, circuit simulation and optimization and their technological implementation. The preliminary results of the test circuit at 4.2 K are demonstrated focusing on the performance. Particularly, we emphasize on the current sensitivity of the circuit based on the output switching probability. The measurement results, show a narrow grayzone width of 0.48 μ A for low-speed operation, demonstrating a higher current sensitivity. Additionally, the designed AQFP circuit exhibits a wide operating margins, further endorsing their potential for high sensitivity based superconducting sensors and scalable interface circuits for quantum electronics.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm −2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimental demonstration of a 3D-XOR gate, the building block cells of which are vertically stacked to save circuit area and wiring length. The measurement results showed reasonable excitation current margins of more than ±16% for the 3D-XOR gate.