Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International Conference on IoT Based Control Networks and Intelligent Systems (ICICNIS)

Design and Quantum Cost Optimization of Ripple Counter using Information Reversal Logic Gates

Kannan Ramakrishnan, K. Vidhya

Published Dec 17, 2024• 1 citation
Publisher

Abstract

Information reversal logic (IRL) has emerged as a promising research area with potential applications across various fields. This research study focuses on designing static circuits, including full adders, subtractors, multiplexers, and comparators, using reversal ripple counters to minimize quantum gate cost. These counters are constructed using CSWAP gates, known for their low quantum gate overhead. IRL is characterized by the one-to-one mapping between input and output patterns, enabling reversible operations. This property aligns with the second law of thermodynamics, preventing heat dissipation. Key concepts in IRL include fan-out and feedback. Due to its low energy consumption, IRL has applications in quantum computing, optics, nanotechnology, and low-power VLSI. This research compares the trash output, quantum gate cost, and gate count of the designed circuits, which are simulated using T-Spice Tools v16.0.

DOI
10.1109/icicnis64247.2024.10823165

Related papers

Novel Methods for Area Optimization in Static Circuits via IRL Interpreter in T-Spice

Kannan Ramakrishnan, K. Vidhya

The Information Reversal Logic (IRL) or reversal logics has garnered considerable attention as a burgeoning research area with potential applications across various domains. This paper focuses on implementing different types of static circuits—such as full-adders, full-subtractors, multiplexers, and comparators—using reversal interpreter circuits with minimal quantum gate costs. The reversal interpreter is built using Asher Peres Gate, Controlled-Swap gate, inverter gate and etc. The benefits of these reversal logic gates are efficiency in minimizing quantum gate usage. Information reversal logic is distinguished by the equivalence of input and output lines, ensuring that for an (n, k) function where ‘n’ number of inputs/outputs equal k’’ number of inputs/outputs. This characteristic facilitates both forward and backward operations, enabling the retrieval of inputs from outputs. Adhering to these conditions is consistent with the thermodynamics, ensuring no heat is dissipated. The principles of fan-out and feedback are essential for logical reversibility. Information reversal logic is applicable in various fields, nanotechnology, and low-power VLSI, optical computing, and quantum computing these are low energy consumption properties. This paper also presents a comparative study of trash outputs, quantum gate costs, and the number of gates used. The designed circuits are implemented and simulated using T-Spice Tools v16.0 software.

Asian Conference on Innovation in Technology (ASIANCON)•Aug 23, 2024•1 citation

A Compact Quantum Cost-Efficient Design of a Reversible Binary Counter

Mubin Ul Haque, Zarrin Tasnim Sworna, Sadia Afrin +1 more

One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.

IEEE International WIE Conference on Electrical and Computer Engineering•Nov 1, 2019•3 citations

A Novel Perspective in Designing a Low Quantum Cost Synchronous Reversible Counters

Shivangi Gupta, Somesh Kumar

Reversible circuits are one of the most promising technologies that allow the reproduction of the inputs from the observed outputs and thus reducing the power dissipation in the form of heat. Many basic and universal logic gates i.e. nand, nor, or, and etc. are irreversible and result in energy consumption during calculations. In the reversible technology, like quantum circuits energy is not consumed during the entire calculation process and these circuits can be used for low-power and quantum communication applications circuits. Counters are considered as one of the most important sequential circuits used in many real-time applications. This paper presents a new approach to design a quantum cost-effective reversible up/down counter circuit using exclusive-or sum of product (ESOP) expressions and TR gates. The proposed counter circuits are simulated in the Xilinx Vivado simulator to verify the functionality of the proposed designs. The comparative study indicates that the proposed counters are superior to the best previous designs in terms of quantum cost (QC) and gate count (GC). Moreover, they are very close to or better than the previously available designs in terms of garbage outputs (GO) and Ancilla inputs (AI).

International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)•Apr 1, 2020•4 citations

Design and Implementation of an Efficient Quantum Cost Optimized Full Adder Using Reversible Logic Gates

S. Bhavani, ,,Vamsi Thota,, Pushkar Nallangadu +3 more

In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.

International Scientific Journal of Engineering and Management•Apr 11, 2026•0 citations

Optimization of Ripple Carry Adder using Quantum Computing

N.Parvatham, Rithiga R, Ruzmina M +1 more

This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.

International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS)•Nov 26, 2025•0 citations

An Efficient 8-Bit Adder/Subtractor Design Utilizing Reversible Logic Techniques

Aruru Sai Kumar, K Charan Kumar, U. Siddhesh +3 more

Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software

International Conference on Electrical Energy Systems (ICEES)•Aug 22, 2024•0 citations
Information reversal logic (IRL) has emerged as a promising research area with potential applications across various fields. This research study focuses on designing static circuits, including full adders, subtractors, multiplexers, and comparators, using reversal ripple counters to minimize quantum gate cost. These counters are constructed using CSWAP gates, known for their low quantum gate overhead. IRL is characterized by the one-to-one mapping between input and output patterns, enabling reversible operations. This property aligns with the second law of thermodynamics, preventing heat dissipation. Key concepts in IRL include fan-out and feedback. Due to its low energy consumption, IRL has applications in quantum computing, optics, nanotechnology, and low-power VLSI. This research compares the trash output, quantum gate cost, and gate count of the designed circuits, which are simulated using T-Spice Tools v16.0.
The Information Reversal Logic (IRL) or reversal logics has garnered considerable attention as a burgeoning research area with potential applications across various domains. This paper focuses on implementing different types of static circuits—such as full-adders, full-subtractors, multiplexers, and comparators—using reversal interpreter circuits with minimal quantum gate costs. The reversal interpreter is built using Asher Peres Gate, Controlled-Swap gate, inverter gate and etc. The benefits of these reversal logic gates are efficiency in minimizing quantum gate usage. Information reversal logic is distinguished by the equivalence of input and output lines, ensuring that for an (n, k) function where ‘n’ number of inputs/outputs equal k’’ number of inputs/outputs. This characteristic facilitates both forward and backward operations, enabling the retrieval of inputs from outputs. Adhering to these conditions is consistent with the thermodynamics, ensuring no heat is dissipated. The principles of fan-out and feedback are essential for logical reversibility. Information reversal logic is applicable in various fields, nanotechnology, and low-power VLSI, optical computing, and quantum computing these are low energy consumption properties. This paper also presents a comparative study of trash outputs, quantum gate costs, and the number of gates used. The designed circuits are implemented and simulated using T-Spice Tools v16.0 software.
One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.
Reversible circuits are one of the most promising technologies that allow the reproduction of the inputs from the observed outputs and thus reducing the power dissipation in the form of heat. Many basic and universal logic gates i.e. nand, nor, or, and etc. are irreversible and result in energy consumption during calculations. In the reversible technology, like quantum circuits energy is not consumed during the entire calculation process and these circuits can be used for low-power and quantum communication applications circuits. Counters are considered as one of the most important sequential circuits used in many real-time applications. This paper presents a new approach to design a quantum cost-effective reversible up/down counter circuit using exclusive-or sum of product (ESOP) expressions and TR gates. The proposed counter circuits are simulated in the Xilinx Vivado simulator to verify the functionality of the proposed designs. The comparative study indicates that the proposed counters are superior to the best previous designs in terms of quantum cost (QC) and gate count (GC). Moreover, they are very close to or better than the previously available designs in terms of garbage outputs (GO) and Ancilla inputs (AI).
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software