The Information Reversal Logic (IRL) or reversal logics has garnered considerable attention as a burgeoning research area with potential applications across various domains. This paper focuses on implementing different types of static circuits—such as full-adders, full-subtractors, multiplexers, and comparators—using reversal interpreter circuits with minimal quantum gate costs. The reversal interpreter is built using Asher Peres Gate, Controlled-Swap gate, inverter gate and etc. The benefits of these reversal logic gates are efficiency in minimizing quantum gate usage. Information reversal logic is distinguished by the equivalence of input and output lines, ensuring that for an (n, k) function where ‘n’ number of inputs/outputs equal k’’ number of inputs/outputs. This characteristic facilitates both forward and backward operations, enabling the retrieval of inputs from outputs. Adhering to these conditions is consistent with the thermodynamics, ensuring no heat is dissipated. The principles of fan-out and feedback are essential for logical reversibility. Information reversal logic is applicable in various fields, nanotechnology, and low-power VLSI, optical computing, and quantum computing these are low energy consumption properties. This paper also presents a comparative study of trash outputs, quantum gate costs, and the number of gates used. The designed circuits are implemented and simulated using T-Spice Tools v16.0 software.
The Information Reversal Logic (IRL) or reversal logics has garnered considerable attention as a burgeoning research area with potential applications across various domains. This paper focuses on implementing different types of static circuits—such as full-adders, full-subtractors, multiplexers, and comparators—using reversal interpreter circuits with minimal quantum gate costs. The reversal interpreter is built using Asher Peres Gate, Controlled-Swap gate, inverter gate and etc. The benefits of these reversal logic gates are efficiency in minimizing quantum gate usage. Information reversal logic is distinguished by the equivalence of input and output lines, ensuring that for an (n, k) function where ‘n’ number of inputs/outputs equal k’’ number of inputs/outputs. This characteristic facilitates both forward and backward operations, enabling the retrieval of inputs from outputs. Adhering to these conditions is consistent with the thermodynamics, ensuring no heat is dissipated. The principles of fan-out and feedback are essential for logical reversibility. Information reversal logic is applicable in various fields, nanotechnology, and low-power VLSI, optical computing, and quantum computing these are low energy consumption properties. This paper also presents a comparative study of trash outputs, quantum gate costs, and the number of gates used. The designed circuits are implemented and simulated using T-Spice Tools v16.0 software.
Information reversal logic (IRL) has emerged as a promising research area with potential applications across various fields. This research study focuses on designing static circuits, including full adders, subtractors, multiplexers, and comparators, using reversal ripple counters to minimize quantum gate cost. These counters are constructed using CSWAP gates, known for their low quantum gate overhead. IRL is characterized by the one-to-one mapping between input and output patterns, enabling reversible operations. This property aligns with the second law of thermodynamics, preventing heat dissipation. Key concepts in IRL include fan-out and feedback. Due to its low energy consumption, IRL has applications in quantum computing, optics, nanotechnology, and low-power VLSI. This research compares the trash output, quantum gate cost, and gate count of the designed circuits, which are simulated using T-Spice Tools v16.0.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software
This work presents the logical reversibility. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations can't erase information and dissipate zero heat. The circuit actually operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power. As the basic elements of any logic circuit, logic gates are used to realize Boolean functions. By combining reversible logic gates, reversible circuits can perform complex logical and arithmetic operations. A one-to-one mapping between inputs and outputs is realized. The logical operations run backwards by cascading a reversible logic gate with its dual (inverse). Reversible circuits are also called lossless circuits, as there is neither energy loss nor information loss. These circuits are very attractive for applications where extremely low power consumption, or heat dissipation, is desirable in areas ranging from communications, low power VLSI (very large-scale integration) technology, optical computing to nanotechnology. Reversible logic found to be very useful in quantum computing where the quantum evolution is inherently reversible.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
Reversible logic is emerging as a promising computing paradigm with applications in ultralow power nanocomputing and emerging nanotechnologies such as quantum computing, quantum dot cellular automata (QCA), optical computing, etc. Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. One of the primary motivations for adopting reversible logic lies in the fact that it can provide a logic design methodology for designing ultra-low power circuits beyond KTln2 limit for those emerging nanotechnologies in which the energy dissipated due to information destruction will be a significant factor of the overall heat dissipation. Further, logic circuits for quantum computers must be built from reversible logic components. Several important metrics need to be considered in the design of reversible circuits the importance of which needs to be discussed. Quantum computers of many qubits are extremely difficult to realize thus the number of qubits in the quantum circuits needs to be minimized. This sets the major objective of optimizing the number of ancilla inputs and the number of the garbage outputs in the reversible logic based quantum circuits. The constant input in the reversible quantum circuit is called the ancilla input, while the garbage output refers to the output which exists in the circuit just to maintain one-to-one mapping but is not a primary or a useful output. The reversible circuit has other important parameters of quantum cost and delay which need to be optimized.