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A Cryo-CMOS 64-Channel Bias Generator IC for Surface Ion Trap

Sungbin Park, Seokchan Song, Keumhyun Kim, Hyegoo Lee, Moonjoo Lee, Jae‐Yoon Sim

Published Sep 9, 2024• 9 citations
Publisher

Abstract

A high-voltage DC bias generator chip is designed to address the scalability challenges of ion trap systems. The circuit employs a single digital-to-analog converter (DAC) to generate 64 channel outputs using time-division multiplexed driving. The chip, fabricated using 180 nm BCDMOS process, produces 64 DC voltages in a range of -10V to 16V at 4 Kelvin(4K) with an 11.06 bit resolution. The chip is verified with a trap of ${ }^{40} \mathbf{C a}^{+}$ ions, showing successful operations of capturing and shuttling the ions.

DOI
10.1109/esserc62670.2024.10719474

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A high-voltage DC bias generator chip is designed to address the scalability challenges of ion trap systems. The circuit employs a single digital-to-analog converter (DAC) to generate 64 channel outputs using time-division multiplexed driving. The chip, fabricated using 180 nm BCDMOS process, produces 64 DC voltages in a range of -10V to 16V at 4 Kelvin(4K) with an 11.06 bit resolution. The chip is verified with a trap of 40Ca+{ }^{40} \mathbf{C a}^{+}40Ca+ ions, showing successful operations of capturing and shuttling the ions.
The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of DC bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this paper presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryo-CMOS demultiplexer and a cryo-CMOS DC DAC have been developed in a 22-nm FinFET process to control a co-developed 2D-array designed with 648 Single Hole Transistors (SHTs). Thanks to the dissipation below 120μ\muμW, the whole system operates at temperatures below 70mK in a custom-built electrical/mechanical infrastructure embedded in a standard singlepulse- tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold (S/H) structures, allowing to store 96 unique bias voltages over a 3V range with a voltage drift between 60μ\muμV/s and 18 mV/s. This work demonstrates a tight integration at mK-temperatures of cryo- CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors towards the large number of qubits required for a practical quantum computer.
Abstract A large-scale ion trap array fabricated using the microelectromechanical systems (MEMS) technology is expected to be a promising device for building a practical quantum computer. Shuttling trapped ions is essential for operating scalable ion trap structures. This paper proposes an ion shuttling method for a MEMS-fabricated surface ion trap. Change of secular frequency of trapping potential can cause heating and subsequent loss of ions. Therefore, direct current voltage sets to form uniform ion trapping potentials around the ions while shuttling are calculated by simulations. A 32-channel digital-to-analog converter system is developed to apply the calculated voltage sets to the electrodes of the MEMS-fabricated surface ion trap. The shuttling process is experimented using trapped 174Yb+ ions. The successful round trip of the ion for 1920 μm is demonstrated using the developed approach.
Surface ion traps have lithographically defined electrode geometries that can be accurately simulated to calculate the voltages needed to store and transport ions, an enabling capability for trapped-ion quantum computing. While these voltage waveforms can be described explicitly as a voltage for each time step, they can be represented more compactly using cubic splines with coefficients calculated from the explicit target waveform. An FPGA would then calculate voltages on-the-fly based on these coefficients with a simple addition loop, sending these values as the input to digital-to-analog converters. Using cubic spline interpolation also increases the flexibility of the control system by simplifying the calibration offsets and time-scaling of waveforms without requiring additional explicit samples. In this paper we show that a single RF system-on-chip can be used to control 100 DAC channels, and propose a system-level architecture that uses scatter gather direct memory access and a highly compact custom data structure to store and generate voltage control waveforms in real-time.
Trapped-ion quantum computers based on the quantum charge-coupled device architecture require on the order of ten trap electrodes per qubit, making the number of vacuum feedthroughs a bottleneck at the system scale. Time-division multiplexed (TDM)-based voltage control for trap electrodes provides a natural route to alleviate this constraint. However, previous studies have been limited to architectural proposals for static trap-potential compensation and room-temperature demonstrations of dynamic-electrode control, leaving cryogenic operation of TDM-based voltage control for static and dynamic electrodes experimentally unexplored. In this study, we develop and cryogenically validate TDM-based voltage control schemes for two distinct electrode classes. For static electrodes used in trap-potential compensation, we implement a 32-channel demultiplexed system operating at approximately 27~K, achieving an effective voltage update rate of 37.5~kHz with an output range of ±10 V\pm10~\mathrm{V}±10 V per channel. For dynamic electrodes used in ion operations, such as shuttling, we implement a four-channel demultiplexed system operating at approximately 14~K, achieving an effective voltage update rate of 1~MHz with a comparable output range. These results establish TDM-based voltage control as a practical approach for both electrode classes, providing a path for mitigating the vacuum feedthrough bottleneck in scalable trapped-ion quantum processors.
Large-scale silicon qubit control requires closer integration of control electronics to qubits at the mK stage of the dilution refrigerator to address the wiring bottleneck. We present a mK demultiplexer chip that uses only two input analog voltages and digital control signals, to provide both DC bias and high-speed voltage pulsing for up to 64 qubit terminals. Integrated with a foundry qubit chip on the same PCB and controlled by a 4 K cryo-CMOS controller, mK cryogenic measurements show multi-terminal characterization of a qubit device.
Independent control of numerous electrodes in quantum charge-coupled device architectures presents a significant challenge for wiring and hardware scalability. To address this issue, we demonstrate a voltage control method based on time-division multiplexing (TDM). This approach utilizes a single high-update-rate digital-to-analog converter (DAC) to sequentially generate control signals for multiple electrodes, thereby reducing both the number of required DACs and associated wiring. We experimentally validate this concept by developing a 10-channel system that operates with only two DACs. The developed TDM-based voltage control system is applied to a surface electrode trap, where we successfully trap a single 40Ca+ ion and demonstrate a simple ion transport primitive. This approach offers a resource-efficient and scalable solution for advanced quantum computing systems based on trapped ions.