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IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates

Sushil Subramanian, Todor Mladenov, Simon Schaal, Bishnu Patra, Lester F. Lampert, Nancy K Robinson, Jeanette M. Roberts, Stefano Pellerano

Published Jun 16, 2024• 12 citations
Publisher

Abstract

Large-scale silicon qubit control requires closer integration of control electronics to qubits at the mK stage of the dilution refrigerator to address the wiring bottleneck. We present a mK demultiplexer chip that uses only two input analog voltages and digital control signals, to provide both DC bias and high-speed voltage pulsing for up to 64 qubit terminals. Integrated with a foundry qubit chip on the same PCB and controlled by a 4 K cryo-CMOS controller, mK cryogenic measurements show multi-terminal characterization of a qubit device.

DOI
10.1109/vlsitechnologyandcir46783.2024.10631530

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Large-scale silicon qubit control requires closer integration of control electronics to qubits at the mK stage of the dilution refrigerator to address the wiring bottleneck. We present a mK demultiplexer chip that uses only two input analog voltages and digital control signals, to provide both DC bias and high-speed voltage pulsing for up to 64 qubit terminals. Integrated with a foundry qubit chip on the same PCB and controlled by a 4 K cryo-CMOS controller, mK cryogenic measurements show multi-terminal characterization of a qubit device.
The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of DC bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this paper presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryo-CMOS demultiplexer and a cryo-CMOS DC DAC have been developed in a 22-nm FinFET process to control a co-developed 2D-array designed with 648 Single Hole Transistors (SHTs). Thanks to the dissipation below 120μ\muμW, the whole system operates at temperatures below 70mK in a custom-built electrical/mechanical infrastructure embedded in a standard singlepulse- tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold (S/H) structures, allowing to store 96 unique bias voltages over a 3V range with a voltage drift between 60μ\muμV/s and 18 mV/s. This work demonstrates a tight integration at mK-temperatures of cryo- CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors towards the large number of qubits required for a practical quantum computer.
A scaled-up quantum computer will require a highly efficient control interface that autonomously manipulates and reads out large numbers of qubits, which for solid-state implementations are usually held at millikelvin (mK) temperatures. Advanced CMOS technology, tightly integrated with the quantum system, would be ideal for implementing such a control interface but is generally discounted on the basis of its power dissipation that leads to heating of the fragile qubits. Here, we demonstrate an ultra low power, CMOS-based quantum control platform that takes digital commands as input and generates many parallel qubit control signals. Realized using 100,000 transistors operating near 100 mK, our platform alleviates the need for separate control lines to every qubit by exploiting the low leakage of transistors at cryogenic temperatures to store charge on floating gate structures that are used to tune-up quantum devices. This charge can then be rapidly shuffled between on-chip capacitors to generate the fast voltage pulses required for dynamic qubit control. We benchmark this architecture on a quantum dot test device, showing that the control of thousands of gate electrodes is feasible within the cooling power of commercially available dilution refrigerators.
Abstract The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.
Spin quantum bits (qubits) in semiconductor silicon quantum dots are one of the most promising candidates for large-scale quantum processor units, since they potentially have higher scalability through advanced semiconductor integration technologies. However, spin qubits require many control signals such as bias voltages, pulses and high-frequency microwaves, which is a major barrier to scale-up of qubits. In current small-scale quantum computer setup, the spin qubits inside the 100 mK cold finger of dilution refrigerator have been controlled by external room temperature instruments via long cables as shown in the left image of Fig. 1. This setup, consisting of fully analog signal transmission between qubits and external instruments, degrades the signal integrity and causes heat injection via cables, making it unsuitable for scalable qubits. Thus, cryogenic CMOS controller solutions have been widely developed to control the qubits from inside the refrigerator by installing the signal generation circuits on 4 K plate as depicted in the middle image of Fig. 1 [1]. This allows for the connection from the external devices to the refrigerator to be made with only digital wirings, which reduces number of cables and heat inflow. However, the distance between the 4 K plate and the 100 mK cold finger is still more than 2 m, degrading the integrity of wideband signals such as pulses.
This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.