Surface ion traps have lithographically defined electrode geometries that can be accurately simulated to calculate the voltages needed to store and transport ions, an enabling capability for trapped-ion quantum computing. While these voltage waveforms can be described explicitly as a voltage for each time step, they can be represented more compactly using cubic splines with coefficients calculated from the explicit target waveform. An FPGA would then calculate voltages on-the-fly based on these coefficients with a simple addition loop, sending these values as the input to digital-to-analog converters. Using cubic spline interpolation also increases the flexibility of the control system by simplifying the calibration offsets and time-scaling of waveforms without requiring additional explicit samples. In this paper we show that a single RF system-on-chip can be used to control 100 DAC channels, and propose a system-level architecture that uses scatter gather direct memory access and a highly compact custom data structure to store and generate voltage control waveforms in real-time.
Surface ion traps have lithographically defined electrode geometries that can be accurately simulated to calculate the voltages needed to store and transport ions, an enabling capability for trapped-ion quantum computing. While these voltage waveforms can be described explicitly as a voltage for each time step, they can be represented more compactly using cubic splines with coefficients calculated from the explicit target waveform. An FPGA would then calculate voltages on-the-fly based on these coefficients with a simple addition loop, sending these values as the input to digital-to-analog converters. Using cubic spline interpolation also increases the flexibility of the control system by simplifying the calibration offsets and time-scaling of waveforms without requiring additional explicit samples. In this paper we show that a single RF system-on-chip can be used to control 100 DAC channels, and propose a system-level architecture that uses scatter gather direct memory access and a highly compact custom data structure to store and generate voltage control waveforms in real-time.
Scalable trapped-ion quantum computing requires fast and reliable transport of ions through complex, segmented radiofrequency trap architectures without inducing excessive motional excitation. We present a numerical toolchain for the systematic generation of time-dependent electrode voltages enabling fast, low-excitation ion shuttling in segmented radiofrequency traps. Based on a model of the trap electrode geometry, the framework combines an electrostatic field solver, efficient unconstrained optimization, waveform postprocessing, and dynamical simulations of ion motion to compute voltage waveforms that realize prescribed transport trajectories while respecting experimental constraints such as voltage limits and bandwidth. The toolchain supports arbitrary trap geometries, including junctions and multi-zone layouts, and allows for the flexible incorporation of optimization objectives. We provide a detailed assessment of the accuracy of the framework by investigating its numerical stability and by comparing measured and predicted secular frequencies. The framework is optimized for numerical performance, enabling rapid numerical prototyping of trap architectures of increasing complexity. As application examples, we apply the framework to the transport of a potential well along a linear, uniformly segmented trap, and we compute a solution for shuttling a potential well around the corner of an X-type trap junction. The presented approach provides an extensible and highly efficient numerical foundation for designing and validating transport protocols in current and next-generation trapped-ion processors.
Scalable trapped-ion quantum computing requires fast and reliable transport of ions through complex, segmented radiofrequency trap architectures without inducing excessive motional excitation. We present a numerical toolchain for the systematic generation of time-dependent electrode voltages enabling fast, low-excitation ion shuttling in segmented radiofrequency traps. Based on a model of the trap electrode geometry, the framework combines an electrostatic field solver, efficient unconstrained optimization, waveform postprocessing, and dynamical simulations of ion motion to compute voltage waveforms that realize prescribed transport trajectories while respecting experimental constraints, such as voltage limits and bandwidth. The toolchain supports arbitrary trap geometries, including junctions and multi-zone layouts, and allows for the flexible incorporation of optimization objectives. We provide a detailed assessment of the accuracy of the framework by investigating its numerical stability and by comparing measured and predicted secular frequencies. The framework is optimized for numerical performance, enabling rapid numerical prototyping of trap architectures of increasing complexity. As application examples, we apply the framework to the transport of a potential well along a linear, uniformly segmented trap, and we compute a solution for shuttling a potential well around the corner of an X-type trap junction. The presented approach provides an extensible and highly efficient numerical foundation for designing and validating transport protocols in current and next-generation trapped-ion processors.
Independent control of numerous electrodes in quantum charge-coupled device architectures presents a significant challenge for wiring and hardware scalability. To address this issue, we demonstrate a voltage control method based on time-division multiplexing (TDM). This approach utilizes a single high-update-rate digital-to-analog converter (DAC) to sequentially generate control signals for multiple electrodes, thereby reducing both the number of required DACs and associated wiring. We experimentally validate this concept by developing a 10-channel system that operates with only two DACs. The developed TDM-based voltage control system is applied to a surface electrode trap, where we successfully trap a single 40Ca+ ion and demonstrate a simple ion transport primitive. This approach offers a resource-efficient and scalable solution for advanced quantum computing systems based on trapped ions.
Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.
The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In conventional QCCD architectures, each trap electrode is controlled via a dedicated digital-to-analog converter (DAC). The conventional approach places an overwhelming demand on electronic resources and wiring complexity. This is because the number of trap electrodes typically exceeds the number of trapped-ion qubits. This study proposes a method that leverages a high-speed DAC to generate time-division multiplexed signals to control a large-scale QCCD trapped-ion quantum processor. The proposed method replaces conventional DACs with a single high-speed DAC that generates the complete voltage waveforms required to control the trap electrodes, thereby significantly reducing the wiring complexity and overall resource requirements. Based on realistic parameters and commercially available electronics, our analysis demonstrates that a QCCD trapped-ion quantum computer with10,000trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs. This is in stark contrast to the10,000dedicated DACs required by conventional control methods. Consequently, employing this approach, we developed a proof-of-concept electronic system and evaluated its analog output performance.
RFSoCs are gaining adoption in many labs for quantum control systems thanks to their compactness and affordability. Making full use of the many components on an RFSoC evaluation board is a challenging engineering problem that must be solved to realize scalable control systems. In this dissertation, I evaluate the performance of various RFSoC components in the context of quantum information science. I present two custom FPGA engines that accelerate and parallelize arbitrary waveform generation. The first engine can be instantiated many times to power low-speed DACs for ion-shuttling trap electrodes. The second engine synthesizes CPMG-XY8n dynamical decoupling pulse sequences on the fly with 203.4ps precision. Both engines consume significantly fewer FPGA resources than conventional alternatives and greatly improve RFSoC viability for quantum control systems.