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Energy efficient and scalable waveform generator engine for qubit control

Diptanshu De

Published Jan 1, 2025• 0 citations
OpenAlex

Abstract

Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.

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Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Superconducting quantum processors are manufactured based on a semiconductor process, which makes qubit integration possible. At the same time, this kind of qubit exhibits high-performance fidelity and decoherence time and requires a programmable arbitrary waveform generator (AWG). This paper presents the implementation of an AWG with a sampling rate of two-gigabit samples per second as well as 16-bit vertical resolution digital-to-analog converters. The AWGs are designed for a scaled-up usage scenario by integrating them with separate microwave devices onto a single backplane. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generation. The jitter of multiple AWG channels is around 10 ps, and the integral nonlinearity and differential nonlinearity are both about 2 least significant bits. This customizable AWG has been used in several superconducting quantum processors, and the result of multiple qubits’ measurement verifies that the AWG is qualified for controlling tens of superconducting qubits.
Superconducting quantum computer is manufactured based on semiconductor process which makes qubits integration possible. At the same time, this kind of qubit exhibits high performance fidelity, de-coherence time, scalability and requires a programmable arbitrary waveform generator (AWG). This paper presents implementation of an AWG which composed of two gigabit samples per second (GSPS) sampling rate, 16 bit vertical resolution digital to analog converters (DACs). The AWG integrated with separate microwave devices onto a metal plate for the scale-up consideration. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generator. The jitter in multiple AWG channels is around 10ps, Integral nonlinearity (INL) as well as differential nonlinearity (DNL) is about 2 LSB, and the qubit performance of the de-coherence time (T2*) achieved 33% promotion over that of a commercial 1 GSPS, 14 bit AWG.
As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.
Execution of quantum algorithms requires a quantum computer architecture with a dedicated quantum instruction set that is capable of supporting translation of workloads into actual quantum operations acting on the qubits. State-of-the-art qubit control setups typically utilize general purpose test instruments such as arbitrary waveform generators (AWGs) to generate a limited set of waveforms or pulses. These waveforms are precomputed and stored prior to execution, and then used to produce control pulses during execution. Besides their prohibitive cost and limited scalability, such instruments suffer from poor programmability due to the absence of an instruction set architecture (ISA). Limited memory for pulse storage ultimately determines the total number of supported quantum operations. In this work, we present a scalable qubit control system that enables efficient qubit control using a flexible ISA to drive a direct digital synthesis (DDS) pipeline producing nanosecond-accurate qubit control signals dynamically. The designed qubit controller provides a higher density of control channels, a scalable design, better programmability, and lower cost compared to state-of-the-art systems. In this work, we discuss the new qubit controller's capabilities, its architecture and instruction set, and present experimental results for coherent qubit control.
Scaling qubit control is a key issue for Large Scale Quantum (LSQ) computing and hardware control systems are increasingly costly in logic and memory resources. We present a newly developed compact Direct Digital Synthesis (DDS) architecture for signal generation for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. Fine control of gate voltages is achieved by on-the-fly generation of very precise ramps. Embedded memory requirements are reduced by orders of magnitude compared to current Arbitrary Waveform Generator (AWG) architectures, removing a major scalability barrier for quantum computing.