As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.
As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.
Scaling qubit control is a key issue for Large Scale Quantum (LSQ) computing and hardware control systems are increasingly costly in logic and memory resources. We present a newly developed compact Direct Digital Synthesis (DDS) architecture for signal generation for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. Fine control of gate voltages is achieved by on-the-fly generation of very precise ramps. Embedded memory requirements are reduced by orders of magnitude compared to current Arbitrary Waveform Generator (AWG) architectures, removing a major scalability barrier for quantum computing.
Signal generators for qubit control and measure-ments play a key role in quantum computers in terms of latency and scalability. Typically, the control pulses are generated by arbitrary waveform generators (AWGs) via preloaded lookup tables. However, this method lacks the flexibility to adjust phase and frequency in complicated programs, such as variational quantum eigensolvers (VAE) or pulse shape optimization al-gorithms. Therefore, we propose a quantum control system composed of a quantum control processor (QCP) and a run-time waveform-configurable signal generator in this work. For the signal generator, we developed a parallelized direct digital synthesis (DDS) structure to adaptively generate waveforms without requiring the entire waveform to be preloaded. The QCP, based on HiSEP-Q, is optimized with a deeper pipelined architecture to increase frequency and match the high bandwidth of signal generators. Additionally, we introduce a synchronization architecture in the QCP to manage uneven delays among different generation threads. Validated on the ZCU216 platform, our system achieves flexible signal generation with an average latency of 20 ns and reduces memory usage by more than 50%.
Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Quantum computing requires scalable control hard-ware capable of generating precise signals and synchronizing operations across large numbers of qubits. However, existing control systems are typically optimized for specific qubit modalities, leading to limited interoperability, high development cost, and poor scalability as device architectures evolve. To address this challenge, a heterogeneous and modular control architecture supporting multiple qubit platforms was previously proposed.This paper evaluates FPGA resource requirements and implementation characteristics of the architecture across four controller variants targeting high-frequency microwave, mid-frequency RF, low-frequency DAC, and digital GPIO applications. The results show that core architectural components—including networking, synchronization, and waveform generation—maintain nearly constant hardware usage across platforms, while resource scaling primarily depends on data throughput requirements rather than architectural complexity.Moreover, the architecture is demonstrated on both high-end FPGAs with high-bandwidth memory and cost-efficient embedded devices, confirming portability and deployment flexibility. These findings validate the feasibility of a unified control framework suitable for heterogeneous quantum systems and large-scale control networks.
In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.