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International Conference on Consumer Electronics

Evaluation of FPGA Resource Requirements for a Scalable Heterogeneous Quantum Control System

Takefumi Miyoshi, Keisuke Koike, Shinichi Morisaka, Yuuya Sugita, T. Sumida, Makoto Negoro, H. Shiomi, Ryutaro Ohira

Published Feb 3, 2026• 0 citations
Publisher

Abstract

Quantum computing requires scalable control hard-ware capable of generating precise signals and synchronizing operations across large numbers of qubits. However, existing control systems are typically optimized for specific qubit modalities, leading to limited interoperability, high development cost, and poor scalability as device architectures evolve. To address this challenge, a heterogeneous and modular control architecture supporting multiple qubit platforms was previously proposed.This paper evaluates FPGA resource requirements and implementation characteristics of the architecture across four controller variants targeting high-frequency microwave, mid-frequency RF, low-frequency DAC, and digital GPIO applications. The results show that core architectural components—including networking, synchronization, and waveform generation—maintain nearly constant hardware usage across platforms, while resource scaling primarily depends on data throughput requirements rather than architectural complexity.Moreover, the architecture is demonstrated on both high-end FPGAs with high-bandwidth memory and cost-efficient embedded devices, confirming portability and deployment flexibility. These findings validate the feasibility of a unified control framework suitable for heterogeneous quantum systems and large-scale control networks.

DOI
10.1109/icce67443.2026.11449817

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Quantum computing requires scalable control hard-ware capable of generating precise signals and synchronizing operations across large numbers of qubits. However, existing control systems are typically optimized for specific qubit modalities, leading to limited interoperability, high development cost, and poor scalability as device architectures evolve. To address this challenge, a heterogeneous and modular control architecture supporting multiple qubit platforms was previously proposed.This paper evaluates FPGA resource requirements and implementation characteristics of the architecture across four controller variants targeting high-frequency microwave, mid-frequency RF, low-frequency DAC, and digital GPIO applications. The results show that core architectural components—including networking, synchronization, and waveform generation—maintain nearly constant hardware usage across platforms, while resource scaling primarily depends on data throughput requirements rather than architectural complexity.Moreover, the architecture is demonstrated on both high-end FPGAs with high-bandwidth memory and cost-efficient embedded devices, confirming portability and deployment flexibility. These findings validate the feasibility of a unified control framework suitable for heterogeneous quantum systems and large-scale control networks.
This paper proposes a control system capable of supporting various qubit platforms by combining control units with different specifications with a lightweight and common interface. To realize quantum computers, several qubit platforms, such as superconducting qubits, neutral atoms, ion traps, and semi-conductor quantum dots, are being researched. Each platform requires different microwave frequencies, channel numbers, intensities, and time scales for control. However, building individual control systems for each platform is not practical from a development cost perspective. Therefore, the standardization of control systems is desired. In practice, common languages and libraries for pulse control software are being developed as both commercial products and open-source projects. However, no widely adopted standardization methods currently exist for the control layer of electrical signals responsible for qubit manipulation. This paper first organizes the challenges in standardizing the control layer of electrical signals. It then proposes an architecture to address these challenges, featuring Ethernet-based unit inter-connections, a synchronization system based on time and pulses, and a lightweight and flexible waveform generation method. The proposed approach allows for practical cost adaptation to various types of qubits by connecting electronic circuits with specifications required for the target qubit platform.
Signal generators for qubit control and measure-ments play a key role in quantum computers in terms of latency and scalability. Typically, the control pulses are generated by arbitrary waveform generators (AWGs) via preloaded lookup tables. However, this method lacks the flexibility to adjust phase and frequency in complicated programs, such as variational quantum eigensolvers (VAE) or pulse shape optimization al-gorithms. Therefore, we propose a quantum control system composed of a quantum control processor (QCP) and a run-time waveform-configurable signal generator in this work. For the signal generator, we developed a parallelized direct digital synthesis (DDS) structure to adaptively generate waveforms without requiring the entire waveform to be preloaded. The QCP, based on HiSEP-Q, is optimized with a deeper pipelined architecture to increase frequency and match the high bandwidth of signal generators. Additionally, we introduce a synchronization architecture in the QCP to manage uneven delays among different generation threads. Validated on the ZCU216 platform, our system achieves flexible signal generation with an average latency of 20 ns and reduces memory usage by more than 50%.
In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.
As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.
Scaling qubit control is a key issue for Large Scale Quantum (LSQ) computing and hardware control systems are increasingly costly in logic and memory resources. We present a newly developed compact Direct Digital Synthesis (DDS) architecture for signal generation for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. Fine control of gate voltages is achieved by on-the-fly generation of very precise ramps. Embedded memory requirements are reduced by orders of magnitude compared to current Arbitrary Waveform Generator (AWG) architectures, removing a major scalability barrier for quantum computing.
This demonstration shows a Quantum-Classical interface (QC-IF) for quantum computing implemented on multiple FPGAs. Quantum computers need a controller to transmit/receive microwave to/from quantum devices. In order to explore various quantum devices, the controller requires flexibility to transmit/receive various wave shapes. In addition to that, scalability is also required for large-scale quantum computers. FPGAs are attractive platforms; however, some challenges exist in implementing QC-IF on FPGAs in terms of required specifications from physics, such as treating data and realizing scalability. This work demonstrates an implementation of QC-IF on FPGA with high bandwidth memory to treat large-volume data in high throughput. Furthermore, the IEEE1588-like clock synchronization mechanism is implemented to make multiple FPGAs synchronized.