This demonstration shows a Quantum-Classical interface (QC-IF) for quantum computing implemented on multiple FPGAs. Quantum computers need a controller to transmit/receive microwave to/from quantum devices. In order to explore various quantum devices, the controller requires flexibility to transmit/receive various wave shapes. In addition to that, scalability is also required for large-scale quantum computers. FPGAs are attractive platforms; however, some challenges exist in implementing QC-IF on FPGAs in terms of required specifications from physics, such as treating data and realizing scalability. This work demonstrates an implementation of QC-IF on FPGA with high bandwidth memory to treat large-volume data in high throughput. Furthermore, the IEEE1588-like clock synchronization mechanism is implemented to make multiple FPGAs synchronized.
This demonstration shows a Quantum-Classical interface (QC-IF) for quantum computing implemented on multiple FPGAs. Quantum computers need a controller to transmit/receive microwave to/from quantum devices. In order to explore various quantum devices, the controller requires flexibility to transmit/receive various wave shapes. In addition to that, scalability is also required for large-scale quantum computers. FPGAs are attractive platforms; however, some challenges exist in implementing QC-IF on FPGAs in terms of required specifications from physics, such as treating data and realizing scalability. This work demonstrates an implementation of QC-IF on FPGA with high bandwidth memory to treat large-volume data in high throughput. Furthermore, the IEEE1588-like clock synchronization mechanism is implemented to make multiple FPGAs synchronized.
Quantum computing has made significant strides, with hardware platforms now advanced enough to tackle the challenges of scaling up to larger and more robust systems. Central to this progression is the interface between quantum processors, comprising isolated qubits, and the classical systems required for their control and readout. As these systems transition from few-qubit devices to fault-tolerant architectures, the complexity of this quantum-classical interaction poses significant engineering challenges. Field-Programmable Gate Arrays (FPGAs) have emerged as an adaptable and efficient solution, offering realtime control, low-latency operations, and seamless integration. This review delves into current FPGA-based platforms, including commercial systems, as well as open-source solutions developed by academic research groups. The architecture, features, and contributions of these platforms to addressing scalability and integration issues are thoroughly examined. Additionally, the review highlights innovations in cryogeniccompatible controllers and explores the potential of Cryo-FPGAs to reduce noise and improve fidelity in quantum systems. By providing a comprehensive analysis of current technologies and identifying opportunities for advancement, this review offers valuable insights for researchers and engineers working to develop scalable quantum computing solutions.
This paper proposes a control system capable of supporting various qubit platforms by combining control units with different specifications with a lightweight and common interface. To realize quantum computers, several qubit platforms, such as superconducting qubits, neutral atoms, ion traps, and semi-conductor quantum dots, are being researched. Each platform requires different microwave frequencies, channel numbers, intensities, and time scales for control. However, building individual control systems for each platform is not practical from a development cost perspective. Therefore, the standardization of control systems is desired. In practice, common languages and libraries for pulse control software are being developed as both commercial products and open-source projects. However, no widely adopted standardization methods currently exist for the control layer of electrical signals responsible for qubit manipulation. This paper first organizes the challenges in standardizing the control layer of electrical signals. It then proposes an architecture to address these challenges, featuring Ethernet-based unit inter-connections, a synchronization system based on time and pulses, and a lightweight and flexible waveform generation method. The proposed approach allows for practical cost adaptation to various types of qubits by connecting electronic circuits with specifications required for the target qubit platform.
Quantum computing requires scalable control hard-ware capable of generating precise signals and synchronizing operations across large numbers of qubits. However, existing control systems are typically optimized for specific qubit modalities, leading to limited interoperability, high development cost, and poor scalability as device architectures evolve. To address this challenge, a heterogeneous and modular control architecture supporting multiple qubit platforms was previously proposed.This paper evaluates FPGA resource requirements and implementation characteristics of the architecture across four controller variants targeting high-frequency microwave, mid-frequency RF, low-frequency DAC, and digital GPIO applications. The results show that core architectural components—including networking, synchronization, and waveform generation—maintain nearly constant hardware usage across platforms, while resource scaling primarily depends on data throughput requirements rather than architectural complexity.Moreover, the architecture is demonstrated on both high-end FPGAs with high-bandwidth memory and cost-efficient embedded devices, confirming portability and deployment flexibility. These findings validate the feasibility of a unified control framework suitable for heterogeneous quantum systems and large-scale control networks.
Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Quantum computing has the potential to revolutionize computation by solving complex problems in a way that classical computers cannot. However, robust and scalable qubit manipulation and control electronics are needed to exploit this potential. Academic efforts in this area are sparse, especially in terms of scalability to hundreds or thousands of qubits. The mod-ular and scalable Quantum Interface Controller (QiController), a room-temperature qubit control architecture, addresses this gap. It is implemented using the Advanced Telecommunications Computing Architecture (ATCA) and its dual-dual star topology. The system has two boards: a “Hub” with an AMD Xilinx RFSoC and a “Node” with peripheral FPGAs and DACs for low-latency flux control. This paper describes the system architecture and firmware developments for multi-board synchronization.