This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.
This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.
This article presents a cryogenic transmon qubit state controller integrated circuit (IC) working at a temperature of 3.5 K for superconducting quantum computing (QC) applications. The qubit state controller IC comprises a polar-modulation-based XY -path driver and a current-steering digital-to-analog converter (DAC)-basedZ-path driver. To generate the XY -path driving pulse with arbitrary envelopes in the frequency range of 4–6 GHz, a switched-capacitor digital power amplifier (DPA) is adopted for amplitude modulation, and an injection locking local oscillator (IL-LO) with a constant-slope digital-to-time-converter (DTC) is used for open-loop phase modulation. With the proposed DPA and IL-LO, the controller can control a qubit with a compact architecture. Fabricated in the 28-nm bulk CMOS process, the controller IC occupies an active die area of 0.9 mm2 per driving channel. The controller achieves a spurious-free dynamic range (SFDR) of 40 dB for a 1 GS/s XY -path driver and an SFDR of 48 dB for a 1 GS/sZ-path driver at 3.5 K. The controller consumes a power of 13.7 mW per qubit. A Rabi experiment at 13.9 MHz, a Ramsey experiment at 3.09 MHz, and a T1 experiment at 15.87μsare conducted using the presented controller IC at 3.5 K to control the transmon superconducting qubit at 10 mK directly.
Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.
In today's mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while the qubit controller hardware works on plates with temperature ranging from a few K to room temperature (RT). The highly-integrated cryo-CMOS qubit controller ASIC that can fully work at 3-4K has been proven to be the most feasible way to scale down the quantum computing system [1–5]. In [1], a pulse modulator is implemented with a limited qubit driving capability, which can only generate fixed length symmetric driving pulse. The controllers in [2], [3] generated the RF driving pulse with a frequency division multiplexing (FDM) mode, with the power dissipation of 192mW/qubit and 46.5mW/qubit, respectively. In [4], a local oscillator (LO) was included to improve the controller integration level, and the chip power consumption was 24.1mW/qubit. An arbitrary waveform generation (AWG) functionality digital design was presented in [5] with a power consumption of 23.1mW/qubit. Nevertheless, with continuously increasing number of qubits to integrate, it remains as one of the major tasks to further reduce the power consumption and size of controller.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.