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IEEE Transactions on Quantum Engineering

Superconducting Through-Substrate Vias on Sapphire Substrates for Quantum Circuits

Kiyotaka Mukasa, Yusuke Nuruki, Hayato Kubo, Yoshihide Narahara, Motohiro Umehara, Kazuyuki Fujie

Published Jan 1, 2024• 3 citations
Publisher

Abstract

Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.

DOI
10.1109/tqe.2024.3416963

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Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.
Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.
Dielectric loss is one of the major decoherence sources of superconducting qubits. Contemporary high-coherence superconducting qubits are formed by material systems mostly consisting of superconducting films on substrate with low dielectric loss, where the loss mainly originates from the surfaces and interfaces. Among the multiple candidates for material systems, a combination of titanium nitride (TiN\mathrm{Ti}\mathrm{N}TiN) film and sapphire substrate has good potential because of its chemical stability against oxidization and its high quality at interfaces. In this work, we report a TiN\mathrm{Ti}\mathrm{N}TiN film deposited onto sapphire substrate achieving low dielectric loss at the material interface. Through the systematic characterizations of a series of transmon qubits fabricated with identical batches of TiN\mathrm{Ti}\mathrm{N}TiN base layers but different geometries of qubit shunting capacitors with various participation ratios of the material interface, we quantitatively extract the loss-tangent value at the substrate-metal interface, which is smaller than $8.9\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}4}$ in a 1-nm disordered layer, and a limiting quality factor of about 7.3 million. By optimizing the interface participation ratio of the two-dimensional (2D) transmon qubit, we reproducibly achieve a quality factor of 5.7 million on average. The best 2D qubits show lifetimes of up to $300\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{s}$ and quality factors achieving 8.1 million. We demonstrate that TiN\mathrm{Ti}\mathrm{N}TiN film on sapphire substrate is an ideal material system for high-coherence superconducting qubits. Our analyses further suggest that the interface dielectric loss around the Josephson-junction part of the circuit could be the dominant limitation of lifetimes for state-of-the-art transmon qubits.
A sapphire machining process integrated with intermediate-scale quantum processors is demonstrated. The process allows through-substrate electrical connections, necessary for low-frequency mode-mitigation, as well as signal-routing, which are vital as quantum computers scale in qubit number, and thus dimension. High-coherence qubits are required to build fault-tolerant quantum computers and so material choices are an important consideration when developing a qubit technology platform. Sapphire, as a low-loss dielectric substrate, has shown to support high-coherence qubits. In addition, recent advances in material choices such as tantalum and titanium-nitride, both deposited on a sapphire substrate, have demonstrated qubit lifetimes exceeding 0.3 ms. However, the lack of any process equivalent of deep-silicon etching to create through-substrate-vias in sapphire, or to inductively shunt large dies, has limited sapphire to small-scale processors, or necessitates the use of chiplet architecture. Here, a sapphire machining process that is compatible with high-coherence qubits is presented. This technique immediately provides a means to scale quantum processing units (QPUs) with integrated mode-mitigation, and provides a route toward the development of through-sapphire-vias, both of which allow the advantages of sapphire to be leveraged as well as facilitating the use of sapphire-compatible materials for large-scale QPUs.
Abstract Realization of practical superconducting quantum computing requires many qubits of long coherence time. Compared to the commonly used Ta deposited on c-plane sapphire, which occasionally form α -Ta (111) grains and β -tantalum grains, high quality Ta (110) film can grow epitaxial on a-plane sapphire because of the atomic relationships at the interface. Well-ordered α - Ta (110) film on wafer-scale a-plane sapphire has been prepared. The film exhibits high residual resistance ratio. Transmon qubits fabricated using these film shows relaxation times exceeding 150 μ s. The results suggest Ta film on a-plane sapphire is a promising choice for long coherence time qubit on wafer scale.