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arXiv:1708.02226

Superconducting Through-Silicon Vias for Quantum Integrated Circuits

Mehrnoosh Vahidpour, William B. O’Brien, Jon Tyler Whyland, Joel Angeles, Jayss Marshall, Diego Scarabelli, Genya Crossman, Kamal Yadav, Yuvraj Mohan, Cat-Vu H. Bui, Vijay Rawat, Russ Renzas, Nagesh Vodrahalli, Andrew J. Bestwick, Chad T. Rigetti

Published Aug 7, 2017• 33 citations
arXivHTMLPDF

Abstract

We describe a microfabrication process for superconducting through-silicon vias appropriate for use in superconducting qubit quantum processors. With a sloped-wall via geometry, we can use non-conformal metal deposition methods such as electron-beam evaporation and sputtering, which reliably deposit high quality superconducting films. Via superconductivity is validated by demonstrating zero via-to-via resistance below the critical temperature of aluminum.

DOI
10.48550/arxiv.1708.02226

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We describe a microfabrication process for superconducting through-silicon vias appropriate for use in superconducting qubit quantum processors. With a sloped-wall via geometry, we can use non-conformal metal deposition methods such as electron-beam evaporation and sputtering, which reliably deposit high quality superconducting films. Via superconductivity is validated by demonstrating zero via-to-via resistance below the critical temperature of aluminum.
This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μm-wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 mQ at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.
Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.
Superconducting through silicon vias are emerging as a key interconnect technology to realise a scalable superconducting quantum computing platform. Integration of semiconductor technology into quantum devices is becoming more common whilst quantum devices are taking advantage of novel combinations of plasma processes and materials to realise more qubits and denser integration. In this letter, plasma processes for fabrication of superconducting niobium nitride TSVs have been developed by means of deep silicon etching, plasma polishing and atomic layer deposition. Key steps were experimentally investigated for their impact on etching and deposition results. The underlying mechanisms have been analysed to optimise the whole process flow. Sidewall topography significantly influenced conformality of niobium nitride deposition into deep features. As a result, high-quality vertical superconducting through silicon vias were obtained with a transition temperature of 10.7 K.
Superconducting through-silicon vias (TSVs), which enable direct signal transmission between circuit layers and reduce spurious coupling, are essential elements in accomplishing a large-scale quantum circuit. However, the widespread adoption of superconducting TSVs has been hindered by fabrication challenges, such as sidewall roughness and complicated process flow. Here, we propose a technique to fabricate superconducting TSVs. With this technique, a single layer of passivated photoresist (PPR) is treated as a hard mask during the Bosch etching process in order to reach an aspect ratio of 20:1 in a 500μm-thick silicon wafer. Compared with other TSV fabrication techniques, using PPR as a hard mask achieves high etching selectivity (80:1), simplifies fabrication process, and yields smooth sidewalls, while remaining compatible with superconducting quantum circuits. To verify superconducting performance, we performed cryogenic measurements on large-diameter TSVs (500μm) that allow uniform aluminum deposition, yielding a critical temperature (TC) of 1.2 K. This technique supports the development of 3D-integrated architectures for superconducting quantum processors, offering a practical pathway toward high-density circuit architectures.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μμμm wide by 20 μμμm long by 200 μμμm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.