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IEEE Electron Device Letters

Plasma Processes for Vertical Niobium Nitride Superconducting Through Silicon Vias

Zhong Ren, Yi Shu, Ciaran T. Lennon, Harm C. M. Knoops, Russ Renzas, Robert H. Hadfield, Mike Cooke

Published Dec 24, 2024• 3 citations
Publisher

Abstract

Superconducting through silicon vias are emerging as a key interconnect technology to realise a scalable superconducting quantum computing platform. Integration of semiconductor technology into quantum devices is becoming more common whilst quantum devices are taking advantage of novel combinations of plasma processes and materials to realise more qubits and denser integration. In this letter, plasma processes for fabrication of superconducting niobium nitride TSVs have been developed by means of deep silicon etching, plasma polishing and atomic layer deposition. Key steps were experimentally investigated for their impact on etching and deposition results. The underlying mechanisms have been analysed to optimise the whole process flow. Sidewall topography significantly influenced conformality of niobium nitride deposition into deep features. As a result, high-quality vertical superconducting through silicon vias were obtained with a transition temperature of 10.7 K.

DOI
10.1109/led.2024.3522184

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Superconducting through silicon vias are emerging as a key interconnect technology to realise a scalable superconducting quantum computing platform. Integration of semiconductor technology into quantum devices is becoming more common whilst quantum devices are taking advantage of novel combinations of plasma processes and materials to realise more qubits and denser integration. In this letter, plasma processes for fabrication of superconducting niobium nitride TSVs have been developed by means of deep silicon etching, plasma polishing and atomic layer deposition. Key steps were experimentally investigated for their impact on etching and deposition results. The underlying mechanisms have been analysed to optimise the whole process flow. Sidewall topography significantly influenced conformality of niobium nitride deposition into deep features. As a result, high-quality vertical superconducting through silicon vias were obtained with a transition temperature of 10.7 K.
Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.
Superconducting through-silicon vias (TSVs), which enable direct signal transmission between circuit layers and reduce spurious coupling, are essential elements in accomplishing a large-scale quantum circuit. However, the widespread adoption of superconducting TSVs has been hindered by fabrication challenges, such as sidewall roughness and complicated process flow. Here, we propose a technique to fabricate superconducting TSVs. With this technique, a single layer of passivated photoresist (PPR) is treated as a hard mask during the Bosch etching process in order to reach an aspect ratio of 20:1 in a 500μm-thick silicon wafer. Compared with other TSV fabrication techniques, using PPR as a hard mask achieves high etching selectivity (80:1), simplifies fabrication process, and yields smooth sidewalls, while remaining compatible with superconducting quantum circuits. To verify superconducting performance, we performed cryogenic measurements on large-diameter TSVs (500μm) that allow uniform aluminum deposition, yielding a critical temperature (TC) of 1.2 K. This technique supports the development of 3D-integrated architectures for superconducting quantum processors, offering a practical pathway toward high-density circuit architectures.
The development of superconducting quantum computing has seen a rapid acceleration in recent years. The number of controllable qubits fabricated on-chip has steadily increased in the pursuit of more computational power. 3D integration has become a key enabling technology for the scalability of these larger systems due to the architectural flexibility it offers, mirroring its impact on conventional electronics. As part of this development, superconducting throughsilicon vias (TSVs) have recently emerged as a method of breaking the wiring plane and routing signals through the substrate as well as for other, more novel, applications such as acting as the capacitive component of a new type of superconducting qubit. This thesis will discuss the simulation, fabrication and measurement of superconducting TSVs. Using ANSYS HFSS electromagnetic simulation software, the geometric parameters of TSV-integrated co-planar waveguides were optimised for the transmission of microwave signals. In addition, a TSV-integrated tunable qubit coupler was simulated and the effect of the device’s geometry on the various capacitances within the device, and in turn on the device’s parameters, such as the charging and Josephson energies, was investigated. As a leading cause of signal degradation in electronic devices, crosstalk should be removed from devices as far as possible. Varying the number and arrangement of grounding TSVs was explored as a strategy for the mitigation of crosstalk between adjacent TSVs and it was found that using 4 ground TSVs to shield the signal TSV resulted in a dramatic reduction in crosstalk, with values of S41 <−140dB at 4GHz. For the fabricated samples, a comparison was made of different Bosch etches used to define the TSVs and it was determined that the ICP power and total etch time were highly influential in the degree of sidewall roughness. Methods of sidewall smoothing were also investigated, with KOH wet etching found to offer near atomic-level smoothness. Finally, the fabricated samples were characterised using, among other methods, cryogenic spectroscopy. A novel application of the method of calibrated cryogenic S-parameter measurement to superconducting TSVs is also presented, with the TSV-integrated co-planar waveguide structure under test exhibiting a peak transmission of -1.44dB.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μμμm wide by 20 μμμm long by 200 μμμm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.