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IEEE International D Systems Integration Conference

Superconducting Titanium Nitride in Through-Silicon Vias for 3D Integration of Qubits

Alexandra Schewski, Ulrich Schaber, Armin Klumpp

Published Sep 25, 2024• 2 citations
Publisher

Abstract

Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.

DOI
10.1109/3dic63395.2024.10830265

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Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.
As one of the mainstream technique routes to implement universal quantum computing, superconducting qubit has been highly anticipated in recent years. However, the current widely-using 2D interconnect forms are not capable to meet the interconnect demand of high integration quantum processor in practical use due to wiring congestion, electromagnetic crosstalk, mechanical stress concentration, limited interior space of dilution refrigerator, etc. Therefore, quantum packaging will also need to be updated from 2D planar to 3D vertical architecture for higher integration density of superconducting qubits. In view of the current chiplet development trends in IC industry, we propose a 3D integration architecture based on the partition strategy of qubit chiplet and bus chiplet for superconducting quantum computing. This chiplet solution respectively utilizes the TSV and microbump structure in superconducting constituent material scheme to achieve low-loss intra-layer and inter-layer connection, which provides a possible technical route for modular large-scale quantum processor. To verify the feasibility of the above architecture, we design a kind of TiN-based TSV test vehicle including daisy chain structure to inspect the stabilization of DC resistance and transmission line structure for evaluation of DC/microwave signal transporting performance during the cool-down process. The TSVs in this test vehicle possess high aspect ratio (10:1,30μm30 \mu\mathrm{m}30μmdiameter) fabricated by DRIE, coating with ∼200nm TiN layer by ALD. Subsequently, Al/TiN planar wiring layer is patterned by secondary lithography and ICP process. Then morphology observation, R.T./cryogenic electrical tests are successively carried out to evaluate the performance of TSV test vehicle. SEM along with EDS reveal that the TiN coating is conformal and defect-free with nearly vertical sidewall profile. Electrical tests show that TSV structures possess satisfactory linear ohmic characteristics and a wide range of process uniformity and repeatability at R.T. Additionally, the DC resistance and S21loss amplitude both exhibit abrupt drop during the cooling process, indicating that certain degree of superconducting transition has probably occurred. Therefore, the TiN-based TSV interposer elaborated in this paper combined with indium-based flip-chip TCB methods provides the possibility to implement 3D quantum integration architecture based on chiplet design.
The development of superconducting quantum computing has seen a rapid acceleration in recent years. The number of controllable qubits fabricated on-chip has steadily increased in the pursuit of more computational power. 3D integration has become a key enabling technology for the scalability of these larger systems due to the architectural flexibility it offers, mirroring its impact on conventional electronics. As part of this development, superconducting throughsilicon vias (TSVs) have recently emerged as a method of breaking the wiring plane and routing signals through the substrate as well as for other, more novel, applications such as acting as the capacitive component of a new type of superconducting qubit. This thesis will discuss the simulation, fabrication and measurement of superconducting TSVs. Using ANSYS HFSS electromagnetic simulation software, the geometric parameters of TSV-integrated co-planar waveguides were optimised for the transmission of microwave signals. In addition, a TSV-integrated tunable qubit coupler was simulated and the effect of the device’s geometry on the various capacitances within the device, and in turn on the device’s parameters, such as the charging and Josephson energies, was investigated. As a leading cause of signal degradation in electronic devices, crosstalk should be removed from devices as far as possible. Varying the number and arrangement of grounding TSVs was explored as a strategy for the mitigation of crosstalk between adjacent TSVs and it was found that using 4 ground TSVs to shield the signal TSV resulted in a dramatic reduction in crosstalk, with values of S41 <−140dB at 4GHz. For the fabricated samples, a comparison was made of different Bosch etches used to define the TSVs and it was determined that the ICP power and total etch time were highly influential in the degree of sidewall roughness. Methods of sidewall smoothing were also investigated, with KOH wet etching found to offer near atomic-level smoothness. Finally, the fabricated samples were characterised using, among other methods, cryogenic spectroscopy. A novel application of the method of calibrated cryogenic S-parameter measurement to superconducting TSVs is also presented, with the TSV-integrated co-planar waveguide structure under test exhibiting a peak transmission of -1.44dB.
Superconducting through silicon vias are emerging as a key interconnect technology to realise a scalable superconducting quantum computing platform. Integration of semiconductor technology into quantum devices is becoming more common whilst quantum devices are taking advantage of novel combinations of plasma processes and materials to realise more qubits and denser integration. In this letter, plasma processes for fabrication of superconducting niobium nitride TSVs have been developed by means of deep silicon etching, plasma polishing and atomic layer deposition. Key steps were experimentally investigated for their impact on etching and deposition results. The underlying mechanisms have been analysed to optimise the whole process flow. Sidewall topography significantly influenced conformality of niobium nitride deposition into deep features. As a result, high-quality vertical superconducting through silicon vias were obtained with a transition temperature of 10.7 K.
Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μμμm wide by 20 μμμm long by 200 μμμm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.