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IEEE Electron Device Letters

Superconducting High-Aspect Ratio Through-Silicon Vias with DC-Sputtered Al for Quantum 3D integration

J. A. Alfaro-Barrantes, Massimo Mastrangeli, David Johannes Thoen, Sven Visser, Juan Bueno, J. J. A. Baselmans, Pasqualina Maria Sarro

Published Jan 1, 2020• 23 citations
Publisher

Abstract

This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μm-wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 mQ at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.

DOI
10.1109/led.2020.2994862

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This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μm-wide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall profile for the axisymmetric vias. Single-via electric resistance as low as 80.44 mQ at room temperature and superconductivity below 1.28 K were measured by a cross-bridge Kelvin resistor structure. This work thus demonstrates the fabrication of functional superconducting interposer layers, suitable for high-density 3D integration of silicon-based quantum computing architectures.
Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using 3D integration with interposers containing through-silicon vias (TSVs), but extending these integration techniques to superconducting quantum systems is challenging. Here, we discuss our approach for realizing high-aspect-ratio superconducting TSVs\textemdash 10 μμμm wide by 20 μμμm long by 200 μμμm deep\textemdash with densities of 100 electrically isolated TSVs per square millimeter. We characterize the DC and microwave performance of superconducting TSVs at cryogenic temperatures and demonstrate superconducting critical currents greater than 20 mA. These high-aspect-ratio, high critical current superconducting TSVs will enable high-density vertical signal routing within superconducting quantum processors.
Superconducting through-silicon vias (TSVs), which enable direct signal transmission between circuit layers and reduce spurious coupling, are essential elements in accomplishing a large-scale quantum circuit. However, the widespread adoption of superconducting TSVs has been hindered by fabrication challenges, such as sidewall roughness and complicated process flow. Here, we propose a technique to fabricate superconducting TSVs. With this technique, a single layer of passivated photoresist (PPR) is treated as a hard mask during the Bosch etching process in order to reach an aspect ratio of 20:1 in a 500μm-thick silicon wafer. Compared with other TSV fabrication techniques, using PPR as a hard mask achieves high etching selectivity (80:1), simplifies fabrication process, and yields smooth sidewalls, while remaining compatible with superconducting quantum circuits. To verify superconducting performance, we performed cryogenic measurements on large-diameter TSVs (500μm) that allow uniform aluminum deposition, yielding a critical temperature (TC) of 1.2 K. This technique supports the development of 3D-integrated architectures for superconducting quantum processors, offering a practical pathway toward high-density circuit architectures.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
As one of the mainstream technique routes to implement universal quantum computing, superconducting qubit has been highly anticipated in recent years. However, the current widely-using 2D interconnect forms are not capable to meet the interconnect demand of high integration quantum processor in practical use due to wiring congestion, electromagnetic crosstalk, mechanical stress concentration, limited interior space of dilution refrigerator, etc. Therefore, quantum packaging will also need to be updated from 2D planar to 3D vertical architecture for higher integration density of superconducting qubits. In view of the current chiplet development trends in IC industry, we propose a 3D integration architecture based on the partition strategy of qubit chiplet and bus chiplet for superconducting quantum computing. This chiplet solution respectively utilizes the TSV and microbump structure in superconducting constituent material scheme to achieve low-loss intra-layer and inter-layer connection, which provides a possible technical route for modular large-scale quantum processor. To verify the feasibility of the above architecture, we design a kind of TiN-based TSV test vehicle including daisy chain structure to inspect the stabilization of DC resistance and transmission line structure for evaluation of DC/microwave signal transporting performance during the cool-down process. The TSVs in this test vehicle possess high aspect ratio (10:1,30μm30 \mu\mathrm{m}30μmdiameter) fabricated by DRIE, coating with ∼200nm TiN layer by ALD. Subsequently, Al/TiN planar wiring layer is patterned by secondary lithography and ICP process. Then morphology observation, R.T./cryogenic electrical tests are successively carried out to evaluate the performance of TSV test vehicle. SEM along with EDS reveal that the TiN coating is conformal and defect-free with nearly vertical sidewall profile. Electrical tests show that TSV structures possess satisfactory linear ohmic characteristics and a wide range of process uniformity and repeatability at R.T. Additionally, the DC resistance and S21loss amplitude both exhibit abrupt drop during the cooling process, indicating that certain degree of superconducting transition has probably occurred. Therefore, the TiN-based TSV interposer elaborated in this paper combined with indium-based flip-chip TCB methods provides the possibility to implement 3D quantum integration architecture based on chiplet design.