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arXiv:2406.09930 · Advanced Materials

Integration of Through‐Sapphire Substrate Machining with Superconducting Quantum Processors

Narendra Acharya, Robert Armstrong, Yashwanth Balaji, Kevin G. Crawford, James C. Gates, Paul C. Gow, Oscar W. Kennedy, Renuka Devi Pothuraju, Kowsar Shahbazi, Connor D. Shelly

Published Jan 19, 2025• 5 citations
arXivHTMLPDF

Abstract

A sapphire machining process integrated with intermediate-scale quantum processors is demonstrated. The process allows through-substrate electrical connections, necessary for low-frequency mode-mitigation, as well as signal-routing, which are vital as quantum computers scale in qubit number, and thus dimension. High-coherence qubits are required to build fault-tolerant quantum computers and so material choices are an important consideration when developing a qubit technology platform. Sapphire, as a low-loss dielectric substrate, has shown to support high-coherence qubits. In addition, recent advances in material choices such as tantalum and titanium-nitride, both deposited on a sapphire substrate, have demonstrated qubit lifetimes exceeding 0.3 ms. However, the lack of any process equivalent of deep-silicon etching to create through-substrate-vias in sapphire, or to inductively shunt large dies, has limited sapphire to small-scale processors, or necessitates the use of chiplet architecture. Here, a sapphire machining process that is compatible with high-coherence qubits is presented. This technique immediately provides a means to scale quantum processing units (QPUs) with integrated mode-mitigation, and provides a route toward the development of through-sapphire-vias, both of which allow the advantages of sapphire to be leveraged as well as facilitating the use of sapphire-compatible materials for large-scale QPUs.

DOI
10.1002/adma.202411780

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A sapphire machining process integrated with intermediate-scale quantum processors is demonstrated. The process allows through-substrate electrical connections, necessary for low-frequency mode-mitigation, as well as signal-routing, which are vital as quantum computers scale in qubit number, and thus dimension. High-coherence qubits are required to build fault-tolerant quantum computers and so material choices are an important consideration when developing a qubit technology platform. Sapphire, as a low-loss dielectric substrate, has shown to support high-coherence qubits. In addition, recent advances in material choices such as tantalum and titanium-nitride, both deposited on a sapphire substrate, have demonstrated qubit lifetimes exceeding 0.3 ms. However, the lack of any process equivalent of deep-silicon etching to create through-substrate-vias in sapphire, or to inductively shunt large dies, has limited sapphire to small-scale processors, or necessitates the use of chiplet architecture. Here, a sapphire machining process that is compatible with high-coherence qubits is presented. This technique immediately provides a means to scale quantum processing units (QPUs) with integrated mode-mitigation, and provides a route toward the development of through-sapphire-vias, both of which allow the advantages of sapphire to be leveraged as well as facilitating the use of sapphire-compatible materials for large-scale QPUs.
Sapphire Machining Integrated with Superconducting Qubits In article number 2411780, Connor D. Shelly and co-workers from OQC and the University of Southampton present the integration of machining of sapphire substrates with superconducting qubits and quantum processors. It is shown that this sapphire machining process is compatible with the production of high-coherence qubits whilst maintaining tight Josephson junction parameter spread. This work provides a route to further scaling of quantum processors on sapphire.
Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes. We present a wafer-scale packaging architecture supporting over 500 qubits on a single 3-inch die. The package is engineered to suppress parasitic RF modes, and to mitigate material loss through simulation-informed design while managing differential thermal contraction to ensure robust operation at millikelvin temperatures. System-level heat-load calculations from a large wiring payload show this package may be operated in commercial dilution refrigerators. Measurements of the qubits loaded into the package show median T1T_1T1​, T2e∼100 μT_{2e} \sim 100~μT2e​∼100 μs ($\sim$100 qubits) alongside readout with median fidelity of 97.5% (54 qubits) and a median qubit temperature of 36 mK (54 qubits). These results validate the performance of these packages and demonstrate that large-scale integration can be achieved without compromising device performance. Finally, we highlight the utility of these packages as a tool for high throughput feedback on qubit figures of merit over large sample sizes, allowing identification of performance outliers in the tails of the coherence distribution, a critical capability for informing fabrication and manufacture of high-quality quantum qubits and quantum processors.