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Advanced Materials

Integration of Through‐Sapphire Substrate Machining with Superconducting Quantum Processors (Adv. Mater. 9/2025)

Narendra Acharya, Robert Armstrong, Yashwanth Balaji, Kevin G. Crawford, James C. Gates, Paul C. Gow, Oscar W. Kennedy, Renuka Devi Pothuraju, Kowsar Shahbazi, Connor D. Shelly

Published Mar 1, 2025• 1 citation
Publisher

Abstract

Sapphire Machining Integrated with Superconducting Qubits In article number 2411780, Connor D. Shelly and co-workers from OQC and the University of Southampton present the integration of machining of sapphire substrates with superconducting qubits and quantum processors. It is shown that this sapphire machining process is compatible with the production of high-coherence qubits whilst maintaining tight Josephson junction parameter spread. This work provides a route to further scaling of quantum processors on sapphire.

DOI
10.1002/adma.202570075

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Sapphire Machining Integrated with Superconducting Qubits In article number 2411780, Connor D. Shelly and co-workers from OQC and the University of Southampton present the integration of machining of sapphire substrates with superconducting qubits and quantum processors. It is shown that this sapphire machining process is compatible with the production of high-coherence qubits whilst maintaining tight Josephson junction parameter spread. This work provides a route to further scaling of quantum processors on sapphire.
A sapphire machining process integrated with intermediate-scale quantum processors is demonstrated. The process allows through-substrate electrical connections, necessary for low-frequency mode-mitigation, as well as signal-routing, which are vital as quantum computers scale in qubit number, and thus dimension. High-coherence qubits are required to build fault-tolerant quantum computers and so material choices are an important consideration when developing a qubit technology platform. Sapphire, as a low-loss dielectric substrate, has shown to support high-coherence qubits. In addition, recent advances in material choices such as tantalum and titanium-nitride, both deposited on a sapphire substrate, have demonstrated qubit lifetimes exceeding 0.3 ms. However, the lack of any process equivalent of deep-silicon etching to create through-substrate-vias in sapphire, or to inductively shunt large dies, has limited sapphire to small-scale processors, or necessitates the use of chiplet architecture. Here, a sapphire machining process that is compatible with high-coherence qubits is presented. This technique immediately provides a means to scale quantum processing units (QPUs) with integrated mode-mitigation, and provides a route toward the development of through-sapphire-vias, both of which allow the advantages of sapphire to be leveraged as well as facilitating the use of sapphire-compatible materials for large-scale QPUs.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Sapphire substrates have recently been recognized for their potential to improve the coherence time of superconducting qubits. However, due to challenges in via fabrication, silicon substrates have been predominantly used for qubits. In this study, we fabricated vias on sapphire substrates using lasers and deposited TiN films by chemical vapor deposition. Cross-sectional views of the via confirmed uniform thickness of the TiN film along the via wall. In addition, the TiN film exhibited a superconducting transition at 4.5 K, demonstrating the successful deposition of a high-quality homogeneous superconducting film. This represents the first example of realizing superconducting through-substrate vias on sapphire substrates, a crucial first step toward achieving the 3-D integration of qubits while maintaining coherence time.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
Abstract As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence ( T 1 , T 2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.