To realize a practical quantum computer using superconducting qubits, engineering the superconducting quantum circuit with precise calculations of qubit energy levels and coupling strengths between components should be conducted. However, as superconducting quantum circuits scale up, identifying the discrepancy between designed and manufactured parameters becomes a major challenge. To estimate changes in key parameters due to the manufacturing errors in superconducting quantum circuits, we introduce a method for modeling manufacturing uncertainty as Gaussian random sampling and perform sensitivity analysis on selected key parameters of the circuit. Our proposed method combines circuit geometry with physics-based finite element analysis simulations to characterize the most sensitive input parameters on the key parameters. Overall, the results demonstrate that the proposed uncertainty and sensitivity analysis method can play an essential role in reducing discrepancies between the design and manufacturing processes in superconducting quantum circuits.
To realize a practical quantum computer using superconducting qubits, engineering the superconducting quantum circuit with precise calculations of qubit energy levels and coupling strengths between components should be conducted. However, as superconducting quantum circuits scale up, identifying the discrepancy between designed and manufactured parameters becomes a major challenge. To estimate changes in key parameters due to the manufacturing errors in superconducting quantum circuits, we introduce a method for modeling manufacturing uncertainty as Gaussian random sampling and perform sensitivity analysis on selected key parameters of the circuit. Our proposed method combines circuit geometry with physics-based finite element analysis simulations to characterize the most sensitive input parameters on the key parameters. Overall, the results demonstrate that the proposed uncertainty and sensitivity analysis method can play an essential role in reducing discrepancies between the design and manufacturing processes in superconducting quantum circuits.
A major challenge in developing quantum computing technologies is to accomplish high precision tasks by utilizing multiplex optimization approaches, on both the physical system and algorithm levels. Loss functions assessing the overall performance of quantum circuits can provide the foundation for many optimization techniques. In this Letter, we use the quadratic error loss and the final-state fidelity loss to characterize quantum circuits. We find that the distribution of computation error is approximately Gaussian, which in turn justifies the quadratic error loss. It is shown that these loss functions can be efficiently evaluated in a scalable way by sampling from Clifford-dominated circuits. We demonstrate the results by numerically simulating 10-qubit noisy quantum circuits with various error models as well as executing 4-qubit circuits with up to ten layers of 2-qubit gates on a superconducting quantum processor. Our results pave the way toward the optimization-based quantum device and algorithm design in the intermediate-scale quantum regime.
This research paper provides an in-depth examination of verification and testing approaches for quantum circuits, focusing on methodologies essential for ensuring the correctness, reliability and operational efficiency of quantum computing systems. Since quantum circuits function on the fundamental principles of superposition and entanglement, they present verification challenges that cannot be effectively addressed using conventional classical testing techniques. As a result, the development of specialized quantum-specific verification strategies has become critically important. The study highlights simulation-based verification as a foundational technique, wherein the outcomes of quantum circuit simulations are systematically compared with results obtained from physical quantum hardware. This process enables the identification of functional inconsistencies and supports iterative refinement of circuit designs. In addition, randomized benchmarking is examined as a key evaluation method for estimating circuit fidelity and quantifying error rates through the application of random gate sequences and performance comparisons against established benchmarks. To further improve system robustness, the research investigates fault-tolerant mechanisms, particularly quantum error correction codes, which play a vital role in minimizing the effects of noise, decoherence and hardware imperfections. The integration of advanced quantum metrology and characterization techniques is also explored, enabling precise measurement and detailed analysis of quantum system behavior. These techniques provide deeper insights into circuit performance and contribute significantly to validation processes. By combining simulation-based verification, randomized benchmarking, fault-tolerant protocols and quantum metrology, this study proposes a comprehensive and reliable framework for quantum circuit verification and testing. The findings contribute to the advancement of dependable quantum technologies and support their growing applications in areas such as cryptography, materials science and other emerging domains.
Quantum computing is advancing rapidly, with superconducting quantum computing (SQC) emerging as one of the most promising platforms for scalable quantum information processing. In contrast to fabrication-focused approaches prevalent in current literature, this work presents a fully simulation-based design and tuning methodology for a small-scale superconducting quantum chip - addressing practical limitations posed by fabrication resource constraints - and consequently excludes physical chip fabrication or real-time performance evaluation (e.g., fidelity and error rate measurements). A meticulous, step-by-step electromagnetic simulation was conducted on the chip, designed using Qiskit Metal and Ansys Electronics, with qubit parameters tuned and verified using the Lumped Oscillator Model (LOM) and Energy Participation Ratio (EPR) methods. The design achieves good parameter convergence with relative tuning error rates (Δ%) below 0.05% after 15 adaptive passes and approximately 50,000 solved mesh elements, yielding an Energy Participation Ratio (EPR) of 91.8 % for the chip substrate (Silicon). Furthermore, the study includes a theoretical comparison between two fundamental qubit-qubit coupling schemes. A key contribution of this work lies in systematically analyzing how geometric variations in qubit design affect critical quantum parameters such as qubit frequencies, anharmonicities, coupling strengths, and dispersive shifts - thereby offering a comprehen-sive, simulation-driven framework for early-stage quantum chip prototyping.
Errors is one major challenge in quantum computing. Presently, general error correction cannot be deployed practically. Other ways to reduce error rates require a precise knowledge about errors. This information is for example used in tooling to improve overall circuit error rates. Doing so can increase the sizes of practical circuits on current systems and therefore allow for larger hybrid high performance computing and quantum computing applications. Calibrations of quantum hardware are used to reduce error rates and report error rates. Because calibrations take a significant amount of time they are typically only run once per day. The error rates found are only valid during calibration as error rates drift, can change rapidly and by a factor of 2–3. In this paper, we show how to use experiments to precisely calculate estimates of error rates for quantum hardware. We show that by running generated structural test circuits, we can model error rates which are closer to the actual hardware error rates than the older calibration data. The produced estimates are vital inputs to several parts of a combined high performance computing and quantum computing system.
Designing a qubit architecture is one of the most critical challenges in achieving scalable and fault-tolerant quantum computing as the performance of a quantum computer is heavily dependent on the coherence times, connectivity and low noise environments. Superconducting qubits have emerged as a frontrunner among many competing technologies, primarily because of their speed of operations, relatively well-developed and offer a promising path toward scalability. Here, we address the challenges of optimizing superconducting qubit hardware through the development of a comprehensive theoretical framework that spans the entire process - from design to the calibration of hardware through quantum gate execution. We develop this framework in four key steps: circuit design, electromagnetic analysis, spectral analysis, and pulse sequencing with calibration. We first refine the qubit's core components - such as capacitance, Josephson junctions, and resonators - to set the foundation for strong performance. The electromagnetic analysis, using the Lumped Oscillator model, allows us to map out the capacitance matrix, ensuring that we minimize spectral dispersion while maximizing coherence times. Following this, we conduct spectral analysis to fine-tune the qubit's frequency spectrum and coherence properties, ensuring that the qubit parameters are optimized. Finally, we focus on pulse sequencing, including pulse-width optimization, DRAG optimization, and randomized benchmarking, to achieve high gate fidelity. We applied this framework to both Transmon and Fluxonium qubits, obtaining results that closely match those found in experimental studies. This work provides a detailed and practical approach to the design, optimization, and calibration of superconducting qubits, contributing to the broader effort to develop scalable quantum computing technologies.
Superconducting quantum bits (qubits) are considered as promising candidates to serve as a platform for a quantum information processor. For the realization of practical quantum computing devices, scalable designs and long lifetimes of qubits are required. In this paper, we present simulation results of “hexagonal” transmon qubit in a superconducting coplanar waveguide (CPW) resonator. We conducted finite-element method simulations considering dielectric losses including the two-level system (TLS) loss to evaluate the performance of the qubit in a practical sense. Then, key parameters of a qubit in superconducting circuits - including lifetime, coupling strength, and energy levels are estimated by the black-box quantization method or by solving circuit quantum-electrodynamics (cQED). Finally, the geometric features and key parameters of the qubit are suggested for typical quantum information processing applications.