Distributed quantum computing is a promising solution for creating large-scale quantum computers. In such scenarios, quantum processing units (QPUs) are connected to each other via quantum and classical links. To increase the performance in such a distributed manner, and due to the fragile nature of quantum bits and their decoherence with time, the impact of classical links such as communication latency and jitter between QPUs shall be considered. Here, we propose a low-latency and time-deterministic FPGA-based network supporting execution of distributed quantum circuits. We focus on transmissions of measurement result and control messages as well as synchronization in a distributed network. We demonstrate that a message is transmitted with 361.60 ns between QPUs using optical Ethernet. Synchronization reaches 9.6 ns precision using only Ethernet frames and can reach 21 ps with an external clock. Further, a use-case example of an Inverse Quantum Fourier Transform is implemented to evaluate the impact in terms of latency for inter-QPU data transfers. Our theoretical error analysis and simulation results show that the latency added by our FPGA-controlled network has a negligible impact on the quantum algorithm performance for practical values of memory decoherence time.
Distributed quantum computing is a promising solution for creating large-scale quantum computers. In such scenarios, quantum processing units (QPUs) are connected to each other via quantum and classical links. To increase the performance in such a distributed manner, and due to the fragile nature of quantum bits and their decoherence with time, the impact of classical links such as communication latency and jitter between QPUs shall be considered. Here, we propose a low-latency and time-deterministic FPGA-based network supporting execution of distributed quantum circuits. We focus on transmissions of measurement result and control messages as well as synchronization in a distributed network. We demonstrate that a message is transmitted with 361.60 ns between QPUs using optical Ethernet. Synchronization reaches 9.6 ns precision using only Ethernet frames and can reach 21 ps with an external clock. Further, a use-case example of an Inverse Quantum Fourier Transform is implemented to evaluate the impact in terms of latency for inter-QPU data transfers. Our theoretical error analysis and simulation results show that the latency added by our FPGA-controlled network has a negligible impact on the quantum algorithm performance for practical values of memory decoherence time.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
Precise time synchronization is a fundamental challenge in distributed quantum systems, with direct implications for secure communication, sensing, and next-generation network technologies. In this study, we present a Field Programmable Gate Array (FPGA)-based implementation of a Time-Correlated Entangled Photons (TCEP) source-based synchronization system, achievingsub-nanosecondaccuracy with timing jitter consistently below 200 ps for a distance up to 20 km. The system leverages the strong temporal correlations inherent in entangled photon pairs to compute synchronization offsets between spatially separated nodes. The design features a modular architecture with optimized kernels for temporal correlation, data aggregation, and normalization, enabling efficient resource utilization and high-throughput performance. Experimental validation demonstrates the FPGA's ability to process photon timestamp data and compute cross-correlation functions significantly faster than traditional CPU-based approaches, achieving execution times in the millisecond range even for large datasets. Our FPGA implementation achieved a consistent$\sim$800 times speedup over CPU, with performance largely unaffected by channel length. Resource utilization analysis highlights the scalability of the design, with the fully integrated system operating at a clock frequency of 397.5 MHz while maintaining efficient use of logic elements, registers, and memory blocks. This hardware-efficient approach provides the timing backbone for next-generation technologies, facilitating advancements in ultra-reliable low-latency communication, distributed quantum computing, quantum-enhanced sensing, navigation, and lays a foundation for forthcoming 6G networks and the quantum internet.
Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
The development of quantum computers, which are effective for problems where computational complexity increases exponentially with input size, such as combinatorial and optimization problems, is progressing rapidly. Quantum computers perform calculations using qubits, which have properties such as superposition and entanglement. However, qubits are known to be extremely susceptible to noise, and the realization of fault-tolerant quantum computing (FTQC), which performs calculations on error-correction codes, is highly anticipated. Our research group is working to achieve quantum error correction for FTQC using an FPGA cluster connected to qubit-control units in a single interconnection network. A large number of physical qubits are necessary to realize a practical error-correction code, and these require a large number of control units. The original plan was to use high-speed Ethernet for the interconnect, but problems arose due to bandwidth saturation caused by increased control units and a large communication delay relative to the qubit coherency time. This paper describes the development of a frame aggregator to address these problems, a dedicated switch for the FPGA cluster, and the results. Both mechanisms offer high scalability with latency equivalent to or lower than that of commercially available Ethernet switches and will make a significant contribution towards the realization of FTQC.
A practical quantum computer of thousands of qubits requires a scalable control system with two fundamental requirements: 1) clock synchronization at the nanosecond scale and 2) low-latency data communication within hundreds of nanoseconds. While a few expensive multi-FPGA commercial control system solutions exist, most open-source solutions are limited to single-board radio frequency system-on-chip (RFSoC). In this work, we present a scalable clock synchronization by implementing minimal Precision Time Protocol and data communication framework for mid-circuit measurement (MCM) using Aurora protocol. The design integrates with QubiC [1] open-source quantum control and measurement system.
Present quantum computers are constrained by limited qubit capacity and restricted physical connectivity, leading to challenges in large-scale quantum computations. Distributing quantum computations across a network of quantum computers is a promising way to circumvent these challenges and facilitate large quantum computations. However, distributed quantum computations require entanglements (to execute remote gates) which can incur significant generation latency and, thus, lead to decoherence of qubits. In this work, we consider the problem of distributing quantum circuits across a quantum network to minimize the execution time. The problem entails mapping the circuit qubits to network memories, including within each computer since limited connectivity within computers can affect the circuit execution time. We provide two-step solutions for the above problem: In the first step, we allocate qubits to memories to minimize the estimated execution time; for this step, we design an efficient algorithm based on an approximation algorithm for the max-quadratic-assignment problem. In the second step, we determine an efficient execution scheme, including generating required entanglements with minimum latency under the network resource and decoherence constraints; for this step, we develop two algorithms with appropriate performance guarantees under certain settings or assumptions. We consider multiple protocols for executing remote gates, viz., telegates and cat-entanglements. With extensive simulations over NetSquid, a quantum network simulator, we demonstrate the effectiveness of our developed techniques and show that they outperform a scheme based on prior work by up to 95%.