A practical quantum computer of thousands of qubits requires a scalable control system with two fundamental requirements: 1) clock synchronization at the nanosecond scale and 2) low-latency data communication within hundreds of nanoseconds. While a few expensive multi-FPGA commercial control system solutions exist, most open-source solutions are limited to single-board radio frequency system-on-chip (RFSoC). In this work, we present a scalable clock synchronization by implementing minimal Precision Time Protocol and data communication framework for mid-circuit measurement (MCM) using Aurora protocol. The design integrates with QubiC [1] open-source quantum control and measurement system.
A practical quantum computer of thousands of qubits requires a scalable control system with two fundamental requirements: 1) clock synchronization at the nanosecond scale and 2) low-latency data communication within hundreds of nanoseconds. While a few expensive multi-FPGA commercial control system solutions exist, most open-source solutions are limited to single-board radio frequency system-on-chip (RFSoC). In this work, we present a scalable clock synchronization by implementing minimal Precision Time Protocol and data communication framework for mid-circuit measurement (MCM) using Aurora protocol. The design integrates with QubiC [1] open-source quantum control and measurement system.
Researchers manipulate and measure quantum processing units via the classical electronics control system. We developed an open-source FPGA-based quantum bit control system called QubiC for superconducting qubits. After years of qubit calibration and testing experience on QubiC 1.0, we recognized the need for mid-circuit measurement and feed-forward capabilities to implement advanced quantum algorithms, and upgraded the system to QubiC 2.0 on an AMD ZCU216 RFSoC evaluation board with all these enriched features. The system uses portable FPGA gateware with a simplified processor to handle commands on-the-fly. For design simplicity and straightforward scaling, we adopted a multi-core distributed architecture, assigning one processor core per qubit. The pulses combine the unique pulse envelope and carrier information specified in a command. Each pulse envelope is pre-stored in the FPGA's block RAMs, ensuring speed and reusability throughout the quantum circuit, while pulse parameters including amplitude, phase, and frequency can be updated from pulse to pulse. The software stack is developed in Python, running on both the FPGA's ARM core and a host computer via XML-RPC. Quantum circuits can be described in a high-level language supporting both pulse-level and native-gate-level programming with high-level control flow constructs, and are compiled into binary commands loaded into the FPGA. With QubiC 2.0, we achieved multi-FPGA synchronization and low-latency data communication, and demonstrated feed-forward experiments on conditional circuits. The system also serves as a platform for artificial intelligence and machine learning driven quantum control, such as FPGA-based real-time quantum state discrimination. The enhanced QubiC system provides researchers with powerful tools to explore and implement advanced quantum algorithms and applications.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Quantum computing requires scalable control hard-ware capable of generating precise signals and synchronizing operations across large numbers of qubits. However, existing control systems are typically optimized for specific qubit modalities, leading to limited interoperability, high development cost, and poor scalability as device architectures evolve. To address this challenge, a heterogeneous and modular control architecture supporting multiple qubit platforms was previously proposed.This paper evaluates FPGA resource requirements and implementation characteristics of the architecture across four controller variants targeting high-frequency microwave, mid-frequency RF, low-frequency DAC, and digital GPIO applications. The results show that core architectural components—including networking, synchronization, and waveform generation—maintain nearly constant hardware usage across platforms, while resource scaling primarily depends on data throughput requirements rather than architectural complexity.Moreover, the architecture is demonstrated on both high-end FPGAs with high-bandwidth memory and cost-efficient embedded devices, confirming portability and deployment flexibility. These findings validate the feasibility of a unified control framework suitable for heterogeneous quantum systems and large-scale control networks.
Control electronics synchronization is of vital importance in scaling up modular quantum computer implementations. It is a critical performance parameter in distributed quantum computing. We present a White Rabbit-based control electronics synchronization architecture using multiple AMD Ultrascale+ architecture-based Radio Frequency System on Chips (RFSoC). White Rabbit ensures precise synchronization across all Radio Frequency Digital-to-Analog Converters (RF-DACs) and Analog-to-Digital Converters (RF-ADCs) in a multi-board architecture and also establishes a classical network between the boards. This synchronization is crucial for generating multiple control signals required for scaling up the number of qubits in quantum computing architectures. By minimizing phase jitter and timing inconsistencies across boards, this approach can significantly improve qubit gate operations, error correction efficiency, and overall system performance.
Quantum computing has the potential to revolutionize computation by solving complex problems in a way that classical computers cannot. However, robust and scalable qubit manipulation and control electronics are needed to exploit this potential. Academic efforts in this area are sparse, especially in terms of scalability to hundreds or thousands of qubits. The mod-ular and scalable Quantum Interface Controller (QiController), a room-temperature qubit control architecture, addresses this gap. It is implemented using the Advanced Telecommunications Computing Architecture (ATCA) and its dual-dual star topology. The system has two boards: a “Hub” with an AMD Xilinx RFSoC and a “Node” with peripheral FPGAs and DACs for low-latency flux control. This paper describes the system architecture and firmware developments for multi-board synchronization.