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International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

An FPGA-based Ethernet Interconnect for Quantum Error Correction

Mizuki Sakata, Yoshito Higa, Yasunori Osana

Published Jun 17, 2026• 0 citations
Publisher

Abstract

The development of quantum computers, which are effective for problems where computational complexity increases exponentially with input size, such as combinatorial and optimization problems, is progressing rapidly. Quantum computers perform calculations using qubits, which have properties such as superposition and entanglement. However, qubits are known to be extremely susceptible to noise, and the realization of fault-tolerant quantum computing (FTQC), which performs calculations on error-correction codes, is highly anticipated. Our research group is working to achieve quantum error correction for FTQC using an FPGA cluster connected to qubit-control units in a single interconnection network. A large number of physical qubits are necessary to realize a practical error-correction code, and these require a large number of control units. The original plan was to use high-speed Ethernet for the interconnect, but problems arose due to bandwidth saturation caused by increased control units and a large communication delay relative to the qubit coherency time. This paper describes the development of a frame aggregator to address these problems, a dedicated switch for the FPGA cluster, and the results. Both mechanisms offer high scalability with latency equivalent to or lower than that of commercially available Ethernet switches and will make a significant contribution towards the realization of FTQC.

DOI
10.1145/3814576.3814589

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The development of quantum computers, which are effective for problems where computational complexity increases exponentially with input size, such as combinatorial and optimization problems, is progressing rapidly. Quantum computers perform calculations using qubits, which have properties such as superposition and entanglement. However, qubits are known to be extremely susceptible to noise, and the realization of fault-tolerant quantum computing (FTQC), which performs calculations on error-correction codes, is highly anticipated. Our research group is working to achieve quantum error correction for FTQC using an FPGA cluster connected to qubit-control units in a single interconnection network. A large number of physical qubits are necessary to realize a practical error-correction code, and these require a large number of control units. The original plan was to use high-speed Ethernet for the interconnect, but problems arose due to bandwidth saturation caused by increased control units and a large communication delay relative to the qubit coherency time. This paper describes the development of a frame aggregator to address these problems, a dedicated switch for the FPGA cluster, and the results. Both mechanisms offer high scalability with latency equivalent to or lower than that of commercially available Ethernet switches and will make a significant contribution towards the realization of FTQC.
Ever increasing number of qubits and improving fidelities pave the way for transitioning from the current NISQ era to the fully fault tolerant quantum computing (FTQC) era. Besides large numbers of high quality qubits, FTQC requires sophisticated quantum error correction (QEC). Here we propose a way to connect the frontend controlling the qubits to the QEC backend in a scalable way using regular Ethernet equipment. We analyze the bandwidth requirements and scaling to large number of qubits. The proposed network allows for a crossvendor connectivity, allowing arbitrary QEC backend systems to be matched with various qubit control frontends.
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Fault-tolerant quantum computing (FTQC) has the potential to reliably execute complex calculations by overcoming the problems raised from the errors and noise inherent in quantum systems. This paper builds upon a 2025 report issued by the National Academy of Technologies of France. After recalling the principles that underly the so-called "quantum advantage," the use of error-correcting codes in the design of fault-tolerant quantum computers is discussed. Also explored are the five most advanced physical technologies that can be used to build such computers and the challenges of scaling up to a sufficient size to run useful applications. After highlighting the limits of monolithic qubit integration, the focus turns to increasing the number of available physical qubits by interconnecting several quantum processing modules. The paper concludes with a discussion of technical and economic environments, their performance benchmarks, and their future coexistence with other computing technologies and with supercomputers.
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Distributed Quantum Computing (DQC) provides a scalable architecture by interconnecting multiple quantum processor units (QPUs).Among various DQC implementations, quantum data centers (QDCs) -where QPUs in different racks are connected through reconfigurable optical switch networks -are becoming feasible in the near term.However, the latency of cross-rack communications and dynamic switch reconfigurations poses unique challenges to communications in QDCs, significantly increasing the overall latency, thereby also reducing the overall fidelity.In this paper, we address these challenges by introducing a novel compiler that optimizes scheduling of communications across the program and network layers.Our evaluation shows that it reduces the overall latency by 8.02× over prior approaches with a small overhead and can be integrated with quantum error correction (QEC) to facilitate fault-tolerant quantum computing (FTQC).We have open-sourced our codes at https://zenodo.org/records/15377656.