Ever increasing number of qubits and improving fidelities pave the way for transitioning from the current NISQ era to the fully fault tolerant quantum computing (FTQC) era. Besides large numbers of high quality qubits, FTQC requires sophisticated quantum error correction (QEC). Here we propose a way to connect the frontend controlling the qubits to the QEC backend in a scalable way using regular Ethernet equipment. We analyze the bandwidth requirements and scaling to large number of qubits. The proposed network allows for a crossvendor connectivity, allowing arbitrary QEC backend systems to be matched with various qubit control frontends.
Ever increasing number of qubits and improving fidelities pave the way for transitioning from the current NISQ era to the fully fault tolerant quantum computing (FTQC) era. Besides large numbers of high quality qubits, FTQC requires sophisticated quantum error correction (QEC). Here we propose a way to connect the frontend controlling the qubits to the QEC backend in a scalable way using regular Ethernet equipment. We analyze the bandwidth requirements and scaling to large number of qubits. The proposed network allows for a crossvendor connectivity, allowing arbitrary QEC backend systems to be matched with various qubit control frontends.
The development of quantum computers, which are effective for problems where computational complexity increases exponentially with input size, such as combinatorial and optimization problems, is progressing rapidly. Quantum computers perform calculations using qubits, which have properties such as superposition and entanglement. However, qubits are known to be extremely susceptible to noise, and the realization of fault-tolerant quantum computing (FTQC), which performs calculations on error-correction codes, is highly anticipated. Our research group is working to achieve quantum error correction for FTQC using an FPGA cluster connected to qubit-control units in a single interconnection network. A large number of physical qubits are necessary to realize a practical error-correction code, and these require a large number of control units. The original plan was to use high-speed Ethernet for the interconnect, but problems arose due to bandwidth saturation caused by increased control units and a large communication delay relative to the qubit coherency time. This paper describes the development of a frame aggregator to address these problems, a dedicated switch for the FPGA cluster, and the results. Both mechanisms offer high scalability with latency equivalent to or lower than that of commercially available Ethernet switches and will make a significant contribution towards the realization of FTQC.
Fault-tolerant quantum computing (FTQC) is a form of universal quantum computing that suppresses physical errors via quantum error correction (QEC). On the other hand, it is expected that the available code distance and the T-gate count will be restricted in the early years of FTQC. Meanwhile, quantum error mitigation (QEM) was recently introduced for suppressing errors in noisy intermediate-scale quantum (NISQ) devices; it improves the computation accuracy of near-term quantum algorithms with its overhead being a greater number of samples. In this work, we integrate QEC and QEM into an efficient FTQC architecture that effectively increases the code distance and T-gate count. Our scheme will dramatically alleviate the required qubit count by tens of percent at the cost of a constant multiplicative sampling overhead within 102 in a wide range of regimes from the post-NISQ era to early FTQC regime, which necessitates the order of from 104 to 1010 logical operations. While it has been widely believed that there do not exist useful applications in post-NISQ regimes due to a chasm between the NISQ and FTQC regimes such as overheads for encoding and T-gate distillations, our scheme can continuously bridge the two distinct regimes.
Quantum systems operate using quantum bits (qubits), which are highly sensitive to external noises and disturbances and they are easily prone to errors. In the Noisy Intermediate-Scale Quantum (NISQ) era, these errors make difficult to build reliable, fault tolerant quantum circuits for real world deployment. This work provides an overview of need for Quantum Error Correction (QEC) in NISQ devices, as qubits commonly get affected by bit-flip, phase-flip, and combined errors that degrades system performance and examines Quantum Error Correction Code (QECC) techniques usage in communication, computation, and quantum multimedia applications such as image and video transmission. In addition, a simple three-qubit repetition circuit is introduced to demonstrate an error-mitigation approach. These findings, also show how QEC improves fidelity, reduces logical errors, and improves noise tolerance. The analysis also identifies challenges and outlines the future research direction aimed at achieving efficient and scalable fault tolerant quantum circuits.
Quantum systems operate using quantum bits (qubits), which are highly sensitive to external noises and disturbances and they are easily prone to errors. In the Noisy Intermediate-Scale Quantum (NISQ) era, these errors make difficult to build reliable, fault tolerant quantum circuits for real world deployment. This work provides an overview of need for Quantum Error Correction (QEC) in NISQ devices, as qubits commonly get affected by bit-flip, phase-flip, and combined errors that degrades system performance and examines Quantum Error Correction Code (QECC) techniques usage in communication, computation, and quantum multimedia applications such as image and video transmission. In addition, a simple three-qubit repetition circuit is introduced to demonstrate an error-mitigation approach. These findings, also show how QEC improves fidelity, reduces logical errors, and improves noise tolerance. The analysis also identifies challenges and outlines the future research direction aimed at achieving efficient and scalable fault tolerant quantum circuits.
Building fault-tolerant quantum computers with large numbers of logical qubits requires both scalable hardware architectures and error-correcting codes that make efficient use of physical qubits. Photonic interconnects address both of these challenges by allowing the physical qubits to be distributed across multiple processors while providing the non-local connectivity necessary to implement resource-efficient codes such as high-rate quantum low-density parity-check (qLDPC) codes. A key requirement for realising this architecture is the ability to perform stabiliser measurements between remote processors, which has not previously been demonstrated experimentally. Here we report the first experimental demonstration of distributed quantum error detection and correction. We generate entanglement between network qubits in two separate trapped-ion processors and use it to perform remote syndrome measurements on data qubits. We first realise a distributed [[2, 1, 1]] repetition code, detecting phase-flip errors on a logical qubit encoded across the two modules in real time and suppressing logical errors. We then combine these mid-circuit syndrome measurements with real-time feedforward to actively correct arbitrary single-qubit Pauli errors on a distributed Bell state. These results provide an experimental foundation for quantum error correction (QEC) across modular quantum architectures.
In recent years, research in quantum computing has largely focused on two approaches: near-term intermediate-scale quantum (NISQ) computing and future fault-tolerant quantum computing (FTQC). A growing body of research into early fault-tolerant quantum computing (EFTQC) is exploring how to utilize quantum computers during the transition between these two eras. However, without agreed-upon characterizations of this transition, it is unclear how best to utilize EFTQC architectures. We argue for the perspective that this transition period will be characterized by a law of diminishing returns in quantum error correction (QEC), where the ability of the architecture to maintain quality operations at scale determines the point of diminishing returns. Two challenges emerge from this picture: how to model this phenomenon of diminishing return of QEC as the performance of devices is continually improving and how to design algorithms to make the most use of these devices. To address these challenges, we present models for the performance of EFTQC architectures, capturing the diminishing returns of QEC. We then use these models to elucidate the regimes in which algorithms suited to such architectures are advantageous. As a concrete example, we show that for the canonical task of phase estimation, in a regime of moderate scalability and using just over one million physical qubits, the “reach” of the quantum computer can be extended (compared to the standard approach) from 90-qubit instances to over 130-qubit instances using a simple early fault-tolerant quantum algorithm, which reduces the number of operations per circuit by a factor of 100 and increases the number of circuit repetitions by a factor of 10 000. This clarifies the role that such algorithms might play in the era of limited-scalability quantum computing. Published by the American Physical Society 2024