In recent years, research in quantum computing has largely focused on two approaches: near-term intermediate-scale quantum (NISQ) computing and future fault-tolerant quantum computing (FTQC). A growing body of research into early fault-tolerant quantum computing (EFTQC) is exploring how to utilize quantum computers during the transition between these two eras. However, without agreed-upon characterizations of this transition, it is unclear how best to utilize EFTQC architectures. We argue for the perspective that this transition period will be characterized by a law of diminishing returns in quantum error correction (QEC), where the ability of the architecture to maintain quality operations at scale determines the point of diminishing returns. Two challenges emerge from this picture: how to model this phenomenon of diminishing return of QEC as the performance of devices is continually improving and how to design algorithms to make the most use of these devices. To address these challenges, we present models for the performance of EFTQC architectures, capturing the diminishing returns of QEC. We then use these models to elucidate the regimes in which algorithms suited to such architectures are advantageous. As a concrete example, we show that for the canonical task of phase estimation, in a regime of moderate scalability and using just over one million physical qubits, the “reach” of the quantum computer can be extended (compared to the standard approach) from 90-qubit instances to over 130-qubit instances using a simple early fault-tolerant quantum algorithm, which reduces the number of operations per circuit by a factor of 100 and increases the number of circuit repetitions by a factor of 10 000. This clarifies the role that such algorithms might play in the era of limited-scalability quantum computing. Published by the American Physical Society 2024
In recent years, research in quantum computing has largely focused on two approaches: near-term intermediate-scale quantum (NISQ) computing and future fault-tolerant quantum computing (FTQC). A growing body of research into early fault-tolerant quantum computing (EFTQC) is exploring how to utilize quantum computers during the transition between these two eras. However, without agreed-upon characterizations of this transition, it is unclear how best to utilize EFTQC architectures. We argue for the perspective that this transition period will be characterized by a law of diminishing returns in quantum error correction (QEC), where the ability of the architecture to maintain quality operations at scale determines the point of diminishing returns. Two challenges emerge from this picture: how to model this phenomenon of diminishing return of QEC as the performance of devices is continually improving and how to design algorithms to make the most use of these devices. To address these challenges, we present models for the performance of EFTQC architectures, capturing the diminishing returns of QEC. We then use these models to elucidate the regimes in which algorithms suited to such architectures are advantageous. As a concrete example, we show that for the canonical task of phase estimation, in a regime of moderate scalability and using just over one million physical qubits, the “reach” of the quantum computer can be extended (compared to the standard approach) from 90-qubit instances to over 130-qubit instances using a simple early fault-tolerant quantum algorithm, which reduces the number of operations per circuit by a factor of 100 and increases the number of circuit repetitions by a factor of 10 000. This clarifies the role that such algorithms might play in the era of limited-scalability quantum computing. Published by the American Physical Society 2024
Progress in fault-tolerant quantum computation (FTQC) has driven the pursuit of practical applications with (EFTQC). These devices, limited in their qubit counts and fault-tolerance capabilities, require algorithms that can accommodate some degrees of error, which are known as EFTQC algorithms. To predict the onset of early quantum advantage, a comprehensive methodology is needed to develop and analyze EFTQC algorithms, drawing insights from both the methodologies of noisy intermediate-scale quantum and traditional FTQC. To address this need, we propose such a methodology for modeling algorithm performance on EFTQC devices under varying degrees of error. As a case study, we apply our methodology to analyze the performance of randomized Fourier estimation (RFE) [Kshirsagar, Katabarwa, and Johnson, ], an EFTQC algorithm for phase estimation. We investigate the runtime performance and the fault-tolerant overhead of RFE in comparison to the traditional quantum phase estimation algorithm. Our analysis reveals that RFE achieves significant savings in physical qubit counts while having a much higher runtime upper bound. We anticipate even greater physical qubit savings when considering more realistic assumptions about the performance of EFTQC devices. By providing insights into the performance trade-offs and resource requirements of EFTQC algorithms, our work contributes to the development of practical and efficient quantum computing solutions on the path to quantum advantage. Published by the American Physical Society 2024
As quantum hardware advances toward fault-tolerant operation, an intermediate stage known as early fault-tolerant quantum computing (EFTQC) is emerging, where partial error correction enables meaningful computation. In this regime, the ability of quantum processors to scale in size and depth has become a crucial factor shaping their achievable performance. This study investigates how finite scalability influences resource requirements for simulating open-shell catalytic systems using Quantum Phase Estimation (QPE). The analysis compares hardware archetypes distinguished by fidelity or operation speed under two representative scalability models. Finite scalability increases qubit and runtime demands yet leaves overall scaling behavior intact, with high-fidelity architectures requiring lower minimum scalability to solve equally sized problems. These effects are largely independent of the chosen scalability model. Extending this framework, we examine runtime competitiveness across hardware and code configurations, incorporating surface-code and quantum Low-Density Parity-Check (LDPC)-based fault tolerance under finite scalability. The results identify operating regimes where high-fidelity architectures remain competitive despite slower gate speeds and show that LDPC codes further expand this regime by reducing space-time overhead. Together, these findings highlight the central role of scalability in quantifying performance and guiding the design of next-generation quantum hardware. Continued progress in scalable architectures will be essential for extending quantum computing to increasingly complex scientific and industrial applications.
Current quantum computing research is divided into two eras: near-term intermediate scaling quantum (NISQ) and fault-tolerant quantum computing (FTQC). There is a significant gap in these both in terms of hardware and algorithms. An important question is “how to transition from NISQ to FTQC”? Some research looks at an intermediate third era of quantum computing, sometimes referred to as “early” fault-tolerant quantum computing (EFTQC). The idea is to establish a trade-off between hardware and algorithmic parameters such that we have limited size circuits, albeit large enough to allow some amount of error-correction at the cost of more number of samples and increased run-time. This also requires adjustment to algorithms for various tasks. One way to do this is to allow the algorithm to tolerate some level of noise in the input. These algorithms are called “robust” quantum algorithms. In this chapter, we will understand what EFTQC means and how we can distinguish between the three eras of quantum computing. Furthermore, we will look at the ideas behind algorithms suitable for EFTQC devices. Lastly, we will look at two examples of robust quantum algorithms for the task of quantum phase estimation.
With quantum computing’s potential to solve classically insurmountable problems, quantum computation has emerged as a transformative paradigm across various fields such as cryptography, materials science, and artificial intelligence. The pursuit of scalable and fault-tolerant quantum computation is at the heart of this evolution. The examination examines the evolution of quantum computing architectures, such as superconducting qubits and quantum error correction (QEC) codes until the recent advancement in Google’s Willow processor. This review highlights this progression. We examine the development of Noisy Intermediate-Scale Quantum (NISQ) devices and the first instances of below-threshold QEC, where an increase in qubit count leads to exponentially lower error rates. By using Willow’s 105-qubit architecture, it is possible to perform real-time error correction on a 77 logical qubit grid and complete random circuit sampling in under five minutes, which would otherwise be an insurmountable task. We examine the way Willow’s method is compared to other quantum platforms and discuss its potential impact on early fault-tolerant quantum computing (EFTQC), scalability, and the future of intelligent quantum systems. In conclusion, the paper highlights some of the open issues and opportunities in quantum hardware, artificial intelligence (AI), and fault-tolerant computation.
The transition from classical to quantum computation marks a shift from deterministic binary logic to a probabilistic, entanglement‑driven framework able to address problems beyond classical reach. Today’s Noisy Intermediate ‑ Scale Quantum era features devices that lack full error correction yet already point toward larger, modular systems designed for fault‑tolerant operation. This paper examines the evolving paradigm shift from classical and NISQ ‑ era machines toward practical fault‑tolerant quantum computing, focusing on how advances in physical qubit technologies, control architectures, and error‑correction strategies are converging to bridge noisy prototypes and scalable, useful machines. We synthesize insights from historical semiconductor scaling trends, contemporary roadmaps from leading institutions and industry, and emerging modular designs with real‑time error decoding. Our analysis shows that while challenges around decoherence, connectivity, and classical co‑processing remain, coordinated progress in hardware, control, and software is laying a coherent foundation for future quantum platforms. The work concludes that quantum computing is maturing into a strategically significant paradigm, poised to redefine the limits of computation in simulation, optimization, and secure communication.
Quantum computing is entering a period in which progress will be shaped as much by advances in computer science as by improvements in hardware. The central thesis of this report is that early fault-tolerant quantum computing shifts many of the primary bottlenecks from device physics alone to computer-science-driven system design, integration, and evaluation. While large-scale, fully fault-tolerant quantum computers remain a long-term objective, near- and medium-term systems will support early fault-tolerant computation with small numbers of logical qubits and tight constraints on error rates, connectivity, latency, and classical control. How effectively such systems can be used will depend on advances across algorithms, error correction, software, and architecture. This report identifies key research challenges for computer scientists and organizes them around these four areas, each centered on a fundamental question.