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IEEE Transactions on Applied Superconductivity

SFQ/DQFP Interface Circuits

Tahereh Jabbari, Eby G. Friedman

Published Apr 5, 2023• 4 citations
Publisher

Abstract

The increasing complexity of hybrid superconductive computing systems has made interface circuits between logic families an issue of growing importance. In this paper, interface circuits between single flux quantum (SFQ) and directly coupled quantum flux parametron (DQFP) logic families to achieve high speed, low power hybrid superconductive computing systems are presented. In the proposed DQFP-to-SFQ interface, margins greater than$\pm$20% for the critical current of the JJs, bias currents, and inductances are exhibited. The margins of the excitation current of the DQFP buffer are$-$38% and +35% with the frequency of the excitation current in the range of 2 GHz to 10 GHz. In the proposed SFQ-to-DQFP interface, the margins are greater than$-$33% and +25%. The margins of the excitation current of the DQFP buffer are$-$50% and +20% for frequencies ranging from 2 GHz to 10 GHz. Since no transformers are required, the physical area of the adiabatic portion of the interface circuits is significantly less than existing interface circuits. The SFQ-to-DQFP interface circuit operates at frequencies approaching 20 GHz. These interface circuits therefore exhibit high parameter margins and operating frequencies while requiring significantly less area as compared to existing interface circuits. The proposed interface circuits support the use of both ultra-low power and high speed logic families in complex hybrid superconductive systems.

DOI
10.1109/tasc.2023.3264575

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The increasing complexity of hybrid superconductive computing systems has made interface circuits between logic families an issue of growing importance. In this paper, interface circuits between single flux quantum (SFQ) and directly coupled quantum flux parametron (DQFP) logic families to achieve high speed, low power hybrid superconductive computing systems are presented. In the proposed DQFP-to-SFQ interface, margins greater than±\pm±20% for the critical current of the JJs, bias currents, and inductances are exhibited. The margins of the excitation current of the DQFP buffer are−-−38% and +35% with the frequency of the excitation current in the range of 2 GHz to 10 GHz. In the proposed SFQ-to-DQFP interface, the margins are greater than−-−33% and +25%. The margins of the excitation current of the DQFP buffer are−-−50% and +20% for frequencies ranging from 2 GHz to 10 GHz. Since no transformers are required, the physical area of the adiabatic portion of the interface circuits is significantly less than existing interface circuits. The SFQ-to-DQFP interface circuit operates at frequencies approaching 20 GHz. These interface circuits therefore exhibit high parameter margins and operating frequencies while requiring significantly less area as compared to existing interface circuits. The proposed interface circuits support the use of both ultra-low power and high speed logic families in complex hybrid superconductive systems.
We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
We investigated interface circuits between a single-flux-quantum (SFQ) circuit and an adiabatic quantum-flux-parametron (AQFP) for their hybrid system. The target frequency of interface circuits is several GHz. The interface circuit that transmits a signal from the SFQ circuit to the AQFP gate (SFQ/AQFP) is realized by combining an SFQ toggle flip-flop (TFF) with the AQFP buffer. The bias margin of the SFQ TFF and the excitation current margin of the SFQ/AQFP interface are 2.47 mV ±24.7% and 1.36 mA ±8.82%, respectively. The interface circuit that transmits a signal from the AQFP to the SFQ circuit (AQFP/SFQ) was designed by using a high-sensitive mutually coupled dc/SFQ converter (MC-dc/SFQ) to detect magnetic flux signal output from the AQFP. The bias margin of the high-sensitive MC-dc/SFQ and the excitation current margin of the AQFP/SFQ are 2.88 mV ±13% and 1.6 mA ±18.8%, respectively. These interface circuits also allow us to use long-distance interconnection based on SFQ passive transmission lines between AQFP gates.
Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.
We have been investigating interface circuits between rapid single-flux-quantum circuits and adiabatic quantum-flux-parametron (AQFP) circuits for use in high-speed low-power hybrid computing system. These interface circuits also enable us to use long-distance interconnections between AQFP gates. In this study, we fabricated and demonstrated AQFP circuits, including long interconnections of passive transmission lines (PTLs), in which the interface circuits were used to convert the signal currents of the AQFP gates into single-flux-quantum pulses traveling along PTLs. The length of each PTL was approximately 4.3 mm. During low-speed measurements, correct operations with wide bias margins were confirmed.
Various superconductor logic families have been proposed to build energy-efficient digital systems. Each logic family has its respective advantages and disadvantages, so in some systems, it is crucial to combine different superconductor logic families. We previously developed adiabatic quantum-flux-parametron (AQFP)/rapid single-flux-quantum (RSFQ) hybrid systems, such as a readout circuit for superconducting photon detectors and a flux-bias circuit for superconducting quantum bits. To facilitate the design of AQFP/RSFQ hybrid systems, here we propose a self-resetting RSFQ-to-AQFP (SR-R2A) interface as a compact signal converter from RSFQ logic into AQFP logic. The SR-R2A interface comprises an RSFQ latch and an AQFP comparator, where the AQFP comparator detects the flux state of the RSFQ latch. A previously proposed RSFQ-to-AQFP (R2A) interface requires single-flux-quantum clock signals to reset the flux state of the RSFQ part in the R2A interface, whereas the SR-R2A interface does not require such signals because the excitation current for the AQFP part also resets the flux state of the RSFQ latch. This feature allows the SR-R2A to be incorporated into AQFP/RSFQ hybrid systems without hardware overhead. We demonstrate an SR-R2A interface chip, fabricated with the AIST 10-kA/cm2Nb high-speed standard process, at 4.2 K in liquid helium. The experimental results indicate reasonably wide operating margins for the excitation currents and bias voltage for the SR-R2A interface.