Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Determination of the Bit Error Rate Due to Thermal Noise Using JoSIM Superconducting Circuit Simulator and the Monte Carlo Method

Tessa Hall, Johannes A. Delport, Coenrad Johann Fourie

Published Mar 2, 2023• 7 citations
Publisher

Abstract

Thermal noise requires careful consideration during the design process of RSFQ circuits since it reduces circuit operating margins and can cause switching errors. Bit error rate (BER) provides a useful means of analysing the effect of this noise on a circuit. With tools developed under the IARPA SuperTools project, we present an implementation of the Monte-Carlo technique for determining BER via simulation. The Monte-Carlo method has been considered previously but not widely implemented due to slow simulation times preventing the determination of small BER values. We use JoSIM – an efficient simulator with SPICE syntax that allows for the simulation of superconducting components and noise sources with improved speed over older superconductor simulators. This speed improvement makes the Monte-Carlo method viable. The simulated BER is plotted against bias current with values in the low-BER region interpolated from the simulated values using MATLAB. We show how the results need to be used as a further qualifier of circuit performance for the characterization of a logic cell library.

DOI
10.1109/tasc.2023.3251940

Related papers

Bit error rate determination of RSFQ logic cells by means of noise analysis of basic network components

Thomas Ortlepp, Hannes Toepfer, Friedrich Uhlmann

The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•3 citations

Playing the ".ac" card in noise analysis of RSFQ circuits

Quentin Herr, M.W. Johnson

Noise-induced bit error rate (BER) is an important design constraint for RSFQ circuits. No method, however, has been reported to calculate the BER of real, multi-junction RSFQ gates. We report such a method that requires only the operating margins and the root-mean-square noise current of the device in question. Noise current is determined using the ".ac" analysis card built into SPICE circuit simulators. As usual, operating margins are also determined using SPICE. These quantities determine BER via the error function, as is appropriate for threshold dynamics. The method is general enough to be applied to any RSFQ gate and even exotic circuits such as those that use passive microstrip signal propagation. Comparison to experimental data indicates that BER in RSFQ circuits does indeed arise strictly from thermal noise.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•4 citations

HTS basic RSFQ cells for an optimal bit-error rate

D. Cassel, Regina Dittmann, B Kuhlmann +4 more

Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.

Superconductor Science and Technology•Feb 19, 2002•8 citations

HTS multilayer technology for optimal bit-error rate RSFQ cells

D. Cassel, Thomas Ortlepp, K. Ilin +7 more

The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•4 citations

Monte Carlo and thermal noise analysis of ultra-high-speed high temperature superconductor digital circuits

Mark Jeffery, P.Y. Xie, Stephen R. Whiteley +1 more

We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.

IEEE Transactions on Applied Superconductivity•Jun 1, 1999•50 citations

Improvement of a bit error rate measuring system for high-temperature superconducting circuits

Masahiro Horibe, Kazuhiro Shimaoka, Y. Tarutani +1 more

We have evaluated and tried to improve the measurement precision of a bit error rate (BER) measuring system for superconducting circuits equipped with a magnetic shield and a cryocooler. A noise model has suggested that the most effective way of improving BER is to reduce the noise figure of the wideband pulse amplifier (WPA). BER measurement using a 3-Gbps, 2/sup 15/-1 pseudo random binary signal showed that by using low-noise WPA (noisefigure=4 dB) a 12.0-mV output voltage is required to obtain a minimum BER of 1.19/spl times/10/sup -15/ (a 10/sup -7/ improvement over the previous system) for a 50 /spl Omega/ standard microstrip. A BER of a La/sub 0.2/Yb/sub 0.9/Ba/sub 1.9/Cu/sub 3/O/sub x//MgO/Au microstrip-line to coplanar-waveguide transition-line converter (MCC) was also measured. It was found that the minimum BER was 4.87/spl times/10/sup -13/ (a 10/sup -5/ improvement over the previous system) when the output voltage was 23.8-mV. However these measured BER values were larger than those expected by the noise model. The cause of the larger measured BER is discussed. A minimum BER of 3.64/spl times/10/sup -55/ in 14.8-mV output voltage for a 50 /spl Omega/ standard microstrip was obtained when the cryo-cooler was not operated (without the noise from a cryo-cooler).

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•3 citations
Thermal noise requires careful consideration during the design process of RSFQ circuits since it reduces circuit operating margins and can cause switching errors. Bit error rate (BER) provides a useful means of analysing the effect of this noise on a circuit. With tools developed under the IARPA SuperTools project, we present an implementation of the Monte-Carlo technique for determining BER via simulation. The Monte-Carlo method has been considered previously but not widely implemented due to slow simulation times preventing the determination of small BER values. We use JoSIM – an efficient simulator with SPICE syntax that allows for the simulation of superconducting components and noise sources with improved speed over older superconductor simulators. This speed improvement makes the Monte-Carlo method viable. The simulated BER is plotted against bias current with values in the low-BER region interpolated from the simulated values using MATLAB. We show how the results need to be used as a further qualifier of circuit performance for the characterization of a logic cell library.
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
Noise-induced bit error rate (BER) is an important design constraint for RSFQ circuits. No method, however, has been reported to calculate the BER of real, multi-junction RSFQ gates. We report such a method that requires only the operating margins and the root-mean-square noise current of the device in question. Noise current is determined using the ".ac" analysis card built into SPICE circuit simulators. As usual, operating margins are also determined using SPICE. These quantities determine BER via the error function, as is appropriate for threshold dynamics. The method is general enough to be applied to any RSFQ gate and even exotic circuits such as those that use passive microstrip signal propagation. Comparison to experimental data indicates that BER in RSFQ circuits does indeed arise strictly from thermal noise.
Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.
The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.
We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.
We have evaluated and tried to improve the measurement precision of a bit error rate (BER) measuring system for superconducting circuits equipped with a magnetic shield and a cryocooler. A noise model has suggested that the most effective way of improving BER is to reduce the noise figure of the wideband pulse amplifier (WPA). BER measurement using a 3-Gbps, 2/sup 15/-1 pseudo random binary signal showed that by using low-noise WPA (noisefigure=4 dB) a 12.0-mV output voltage is required to obtain a minimum BER of 1.19/spl times/10/sup -15/ (a 10/sup -7/ improvement over the previous system) for a 50 /spl Omega/ standard microstrip. A BER of a La/sub 0.2/Yb/sub 0.9/Ba/sub 1.9/Cu/sub 3/O/sub x//MgO/Au microstrip-line to coplanar-waveguide transition-line converter (MCC) was also measured. It was found that the minimum BER was 4.87/spl times/10/sup -13/ (a 10/sup -5/ improvement over the previous system) when the output voltage was 23.8-mV. However these measured BER values were larger than those expected by the noise model. The cause of the larger measured BER is discussed. A minimum BER of 3.64/spl times/10/sup -55/ in 14.8-mV output voltage for a 50 /spl Omega/ standard microstrip was obtained when the cryo-cooler was not operated (without the noise from a cryo-cooler).