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IEEE Transactions on Applied Superconductivity

Playing the ".ac" card in noise analysis of RSFQ circuits

Quentin Herr, M.W. Johnson

Published Jun 1, 2003• 4 citations
Publisher

Abstract

Noise-induced bit error rate (BER) is an important design constraint for RSFQ circuits. No method, however, has been reported to calculate the BER of real, multi-junction RSFQ gates. We report such a method that requires only the operating margins and the root-mean-square noise current of the device in question. Noise current is determined using the ".ac" analysis card built into SPICE circuit simulators. As usual, operating margins are also determined using SPICE. These quantities determine BER via the error function, as is appropriate for threshold dynamics. The method is general enough to be applied to any RSFQ gate and even exotic circuits such as those that use passive microstrip signal propagation. Comparison to experimental data indicates that BER in RSFQ circuits does indeed arise strictly from thermal noise.

DOI
10.1109/tasc.2003.813926

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IEEE Transactions on Applied Superconductivity•Mar 1, 2001•9 citations
Noise-induced bit error rate (BER) is an important design constraint for RSFQ circuits. No method, however, has been reported to calculate the BER of real, multi-junction RSFQ gates. We report such a method that requires only the operating margins and the root-mean-square noise current of the device in question. Noise current is determined using the ".ac" analysis card built into SPICE circuit simulators. As usual, operating margins are also determined using SPICE. These quantities determine BER via the error function, as is appropriate for threshold dynamics. The method is general enough to be applied to any RSFQ gate and even exotic circuits such as those that use passive microstrip signal propagation. Comparison to experimental data indicates that BER in RSFQ circuits does indeed arise strictly from thermal noise.
Thermal noise requires careful consideration during the design process of RSFQ circuits since it reduces circuit operating margins and can cause switching errors. Bit error rate (BER) provides a useful means of analysing the effect of this noise on a circuit. With tools developed under the IARPA SuperTools project, we present an implementation of the Monte-Carlo technique for determining BER via simulation. The Monte-Carlo method has been considered previously but not widely implemented due to slow simulation times preventing the determination of small BER values. We use JoSIM – an efficient simulator with SPICE syntax that allows for the simulation of superconducting components and noise sources with improved speed over older superconductor simulators. This speed improvement makes the Monte-Carlo method viable. The simulated BER is plotted against bias current with values in the low-BER region interpolated from the simulated values using MATLAB. We show how the results need to be used as a further qualifier of circuit performance for the characterization of a logic cell library.
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
We measured the bit-error rate (BER) of an RS latch, a clocked SFQ circuit. A digital error-detection circuit was used to detect BER in the range unity to 10/sup -13/; below 10/sup -7/, the circuit was operated with a 12 GHz on-chip clock. BER was measured as a function of control current; both positive and negative control current was applied, leading to two distinct modes of error incidence. The error function curves extrapolate to 10/sup -80/ for optimal control current at a temperature of 5.5 K. Measurements were repeated over the range 3-7 K. Comparison to theoretical error-function estimates of BER indicate that the noise is strictly thermal.
Abstract A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting Single Flux Quantum logic circuits. Simulations are used to evaluate the multidimensional Gaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free Reciprocal Quantum Logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6%–23% of the junction plasma frequency at a modest clock rate of 3.4 GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.
Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.
A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.