Alternative computing such as stochastic computing and bio-inspired computing holds promise for overcoming the limitations of von Neumann computers. However, one difficulty in the implementation of such alternative computing is the need for a large number of random bits at the same time. To address this issue, we propose a scalable true-random-number generating scheme that we refer to as XORing shift registers (XSR). XSR generates multiple uncorrelated true random bitstreams using only two true random number generators as entropy sources and can thus be implemented by a variety of logic devices. Toward superconducting alternative computing, we implement XSR using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. Furthermore, to demonstrate its performance, we design and observe an AQFP-based XSR circuit that generates four random bitstreams in parallel. The results of the experiment confirm that the bitstreams generated by the XSR circuit exhibit no autocorrelation and that there is no correlation between the bitstreams.
Alternative computing such as stochastic computing and bio-inspired computing holds promise for overcoming the limitations of von Neumann computers. However, one difficulty in the implementation of such alternative computing is the need for a large number of random bits at the same time. To address this issue, we propose a scalable true-random-number generating scheme that we refer to as XORing shift registers (XSR). XSR generates multiple uncorrelated true random bitstreams using only two true random number generators as entropy sources and can thus be implemented by a variety of logic devices. Toward superconducting alternative computing, we implement XSR using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. Furthermore, to demonstrate its performance, we design and observe an AQFP-based XSR circuit that generates four random bitstreams in parallel. The results of the experiment confirm that the bitstreams generated by the XSR circuit exhibit no autocorrelation and that there is no correlation between the bitstreams.
We propose a true random number generator (TRNG) based on adiabatic quantum-flux-parametron (AQFP) logic. This AQFP TRNG corresponds to an AQFP buffer chain with the input current removed, which enables the generation of random bits via thermal fluctuation. To realize ultralow autocorrelation, several isolation inductors are inserted between adjacent buffers in the AQFP TRNG, thereby reducing the impact of the back action between buffers. We design and fabricate an AQFP TRNG using the AIST 10 kA/cm2Nb high-speed standard process and evaluate the quality of the generated random bit streams. For a 217-bit random stream obtained from the AQFP TRNG at 100 kHz, the autocorrelation function is 5.00 × 10-3. Furthermore, we evaluate a 220-bit random stream from the AQFP TRNG using a statistical test suite provided by the National Institute of Standards and Technology. The bit stream passed 14 out of 15 tests, which suggests that the proposed AQFP TRNG can be used for applications such as stochastic computing and stochastic local search algorithms.
Quantum processors have the potential to accelerate specific computing tasks but are difficult to scale up due to engineering limitations, such as the number of available cables and cooling power for dilution refrigerators for quantum bits (qubits). Hence, it is very important to develop scalable, energy-efficient interface circuits that can control many qubits via a few control lines inside a dilution refrigerator. One of the most important interface circuits is the flux controller (FC), which generates arbitrary dc flux bias to adjust the characteristics of component devices such as qubits. In this paper, we propose and demonstrate FCs using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. We develop two types of FCs: the AQFP FC and the AQFP/single-flux-quantum (AQFP/SFQ) FC. Both FCs require only a few control lines and have extremely small power dissipation, thus exhibiting high scalability. Furthermore, the AQFP/SFQ FC can control flux bias using ballistic SFQ transmission, which is crucial for integration with qubits. As a proof of concept, we demonstrate AQFP and AQFP/SFQ FCs at 4.2 K, fabricated by the AIST high-speed standard process. Our results indicate that AQFP logic is highly suitable for use as qubit interface circuits for very large-scale quantum processors, especially from the viewpoint of the control line count, power dissipation, and amount of supply currents.
Complementary metal-oxide-semiconductor (CMOS) circuit technology has sustainedthe exponential growth of computing power for more than 20 years. However, it hasbeen estimated that the power consumption of a next-generation supercomputer willexceed the power supplied from a single power plant. This indicates the need to dramaticallyimprove the energy efficiency of logic devices to achieve future high-endcomputers.As an extremely energy-efficient logic, we proposed and have been investigatingadiabatic quantum-flux-parametron (AQFP) devices. Due to adiabatic switching operations,its bit energy (energy dissipation per bit) can go below Ic 0, where Ic is acritical current of a Josephson junction and 0 is a single-flux-quantum (SFQ). Ic 0corresponds to the energy dissipated at every 2 phase transition in conventional nonadiabaticsuperconductor logics.We have two objectives in this study. One is to reveal physical energy bounds oncomputation through investigation of the energy efficiency of AQFP logic. The otheris to develop fundamental circuits necessary for energy-efficient computing systemsusing AQFP logic.First, we numerically and experimentally demonstrated the sub-Ic 0 bit-energyoperations of AQFP gates to show that AQFP gates operate in adiabatic modes. Weinvestigated the dependence of energy dissipation and operation margins on circuitparameters. After optimizing the parameters, we calculated the bit energy and the biterror rate at 4.2 K to verify the sub-Ic 0 bit-energy operations at a finite temperature.Additionally, we measured the bit energy of an AQFP gate using a superconductorresonator-based method.Secondly, we numerically demonstrated the sub-kBT bit-energy operations, wherekB is the Boltzmann constant and T is temperature, to show that AQFP gates can operatebeyond thermodynamic energy bounds. We investigated the dependence of energydissipation on operation frequencies and damping conditions of Josephson junctions.By using underdamped junctions, we confirmed the sub-kBT bit-energy operationsat a finite temperature thorough circuit simulation. This result indicates that thereis no minimum energy dissipation required for the operations of AQFP gates unlessthe entropy of the system decreases, which corresponds to the Landauer’s argument on the minimum energy dissipation for computation. Also, we discussed quantummechanicalenergy bounds and experimentally demonstrated AQFP gates with underdampedjunctions.Additionally, we investigated reversible computing using AQFP logic with underdampedjunctions, in order to deal with an important but unresolved question: “Isreversible computing achievable by using practical devices?” We built a purely reversiblegate by using AQFP gates, which we designated as the reversible quantumflux-parametron (RQFP) gate. We calculated its energy dissipation and confirmed thatthere is no minimum energy dissipation for reversible logic operations using RQFPgates. To the best of our knowledge, these are the first calculation results that show nominimum energy dissipation in reversible computing that use practical circuit structures.Moreover, our experimental results have demonstrated the logical and physicalreversibility of the RQFP gate. We believe that this is the first demonstration thatshows both logical and physical reversibility using practical devices.Finally, we proposed a novel energy-efficient latch for AQFP logic, which we designatedas the quantum-flux-latch (QFL). Latches are necessary circuitries in largecomputing systems but had been missing in AQFP logic. We discussed its energyefficiency through simulation and experimentally demonstrated correct operations ofthe QFL and a 1-bit shift register using QFLs. Also, we proposed high-speed test circuitsusing QFLs and experimentally demonstrated logic operations of AQFP circuitsat high speed.We strongly believe that our results showed the extremely high energy efficiency ofAQFP logic. These results will move the AQFP logic to practical usage as extremelyenergy-efficient integrated circuits.
Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several levels of TLs by using passive splitters, creating multiple leaves at the final level. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising four blocks with data interconnections between each other, and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.