Abstract Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several levels of TLs by using passive splitters, creating multiple leaves at the final level. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising four blocks with data interconnections between each other, and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.
Abstract Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several levels of TLs by using passive splitters, creating multiple leaves at the final level. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising four blocks with data interconnections between each other, and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.
Adiabatic quantum-flux-parametron (AQFP) logic is a highly energy-efficient superconductor logic family. Traditionally, AQFP circuits have relied on the four-phase clocking scheme, which uses a pair of ac current sources with a 90° phase difference. The operation of each logic gate thus takes a quarter clock cycle, leading to a relatively long latency for some applications. In this Letter, we propose a low-latency clocking scheme for AQFP logic based on microwave power dividers (PDs). The whole circuit is powered by a single excitation current, which is equally split for each logic stage by a serial-type PD. As a result, the latency between adjacent logic stages is determined by the transmission line length (propagation delay) inside the PD, which can be much shorter than a quarter clock cycle. Note that the low-latency performance is independent of the horizontal length of the AQFP circuit, and thus, the proposed clocking scheme is applicable to large-scale designs where a large number of gates are horizontally placed in a single stage. For validation, several numerical simulations are conducted and a six-stage AQFP test circuit is demonstrated using the proposed power-dividing clocking scheme (with a designed latency of 20 ps per gate) at a temperature of 4.2 K.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.
Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic family. Since AQFP gates are powered and clocked by ac excitation current, it is difficult to make feedback loops in datapaths at high clock frequencies, which should be solved in order to design large-scale digital circuits such as microprocessors. In this paper, we propose a novel clocking scheme, which we designate as hybrid clocking, to make feedback loops in AQFP datapaths at high clock frequencies. In hybrid clocking, an entire datapath is divided into two parts: the concurrent-flow block and the counter-flow block. In this way, clock skews are avoided, so that feedback closure can be made independent of clock frequencies. We conduct the simulation of an AQFP buffer chain adopting hybrid clocking at 5 GHz to demonstrate that feedback can be made at high clock frequencies. Then, we investigate the maximum allowable clock skew between AQFP gates using this approach, which is important for physical layout design. We find that, with some modifications to the amplitude of excitation current, the maximum allowable clock skew of 47 ps is achieved at 5 GHz. This large allowable clock skew ensures that hybrid clocking can be adopted in large-scale AQFP datapaths.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.