Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Vehicular Technology

Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes

Anuj Verma, Rahul Shrestha

Published Sep 2, 2022• 38 citations
Publisher

Abstract

This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10$^{-5}$at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$-$26112 bits and 1/3$-$8/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.77$\mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.

DOI
10.1109/tvt.2022.3203802

Related papers

Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture

Anuj Verma, Rahul Shrestha

This brief proposes hardware-friendly QC-LDPC decoding algorithm with layered scheduling based on new logarithmic-likelihood-ratio compound (LLRC) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations. This decoder has been designed based on the 5G-NR specifications, supporting code-lengths and code-rates in the ranges of 26112-10368 bits and 1/3-8/9, respectively. Performance analysis has shown that suggested LLRC-segregation based decoding algorithm delivers adequate FER of 10-5between 1 to 6.5 dB of SNR range. Furthermore, proposed QC-LDPC decoder is post-route simulated and implemented on the FPGA platform. It operates at a maximum clock frequency of 135 MHz and delivers a peak throughput of 11.02 Gbps. Eventually, comparison with relevant works shows that our decoder delivers 2.2× higher throughput and 8.3× better hardware-efficiency than the state-of-the-art implementations.

IEEE Transactions on Circuits & Systems II Express Briefs•Apr 9, 2021•11 citations

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Tram Thi Bao Nguyen, Tuy Tan Nguyen, Hanho Lee

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Electronics•Feb 22, 2021•41 citations

New and efficient decoding architecture for Quasi-Cyclic LDPC codes

Zhiming Fan, Zhanji Wu, Hui Che +1 more

In this paper, a new and efficient decoding architecture, Single-Scan Layer Decoding (SLD), is realized in FPGA for multi-rate Quasi-Cyclic LDPC (QC-LDPC) codes. The SLD algorithm simplifies the nodes updating process and messages storing process of the offset min-sum algorithm, speeding up the decoding process and reducing nearly a half of resources consumption. Besides, the SLD algorithm, introducing the semi-parallel architecture into decoding architecture, can increase the convergence rate by 2X and decrease the interconnect complexity of hardware implementation. For multi-rate QC-LDPC Codes in 802.11.n, comparing with float-point software implementation, the degradations of the fixed-point SLD algorithm with 10 iterations in FPGA are all less than 0.ldB and the throughput of different code rates are all above 100Mbps.

International Conference on Communications and Networking in China (ChinaCom)•Aug 1, 2014•0 citations

An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz +1 more

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

Computers•Aug 14, 2024•11 citations

A Comparative Study on High Performance of LDPC Decoders for 5G Applications

Y. Sugandhi Naidu, P. Vijaya Lakshmi

5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.

Journal of Engineering Science and Technology Review•Jun 1, 2026•0 citations

A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard

Anuj Verma, Rahul Shrestha

In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.

IEEE International Symposium on Circuits and Systems proceedings•Sep 29, 2020•22 citations
This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10−5^{-5}−5at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368−-−26112 bits and 1/3−-−8/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.77μ\muμs while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.
This brief proposes hardware-friendly QC-LDPC decoding algorithm with layered scheduling based on new logarithmic-likelihood-ratio compound (LLRC) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations. This decoder has been designed based on the 5G-NR specifications, supporting code-lengths and code-rates in the ranges of 26112-10368 bits and 1/3-8/9, respectively. Performance analysis has shown that suggested LLRC-segregation based decoding algorithm delivers adequate FER of 10-5between 1 to 6.5 dB of SNR range. Furthermore, proposed QC-LDPC decoder is post-route simulated and implemented on the FPGA platform. It operates at a maximum clock frequency of 135 MHz and delivers a peak throughput of 11.02 Gbps. Eventually, comparison with relevant works shows that our decoder delivers 2.2× higher throughput and 8.3× better hardware-efficiency than the state-of-the-art implementations.
This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.
In this paper, a new and efficient decoding architecture, Single-Scan Layer Decoding (SLD), is realized in FPGA for multi-rate Quasi-Cyclic LDPC (QC-LDPC) codes. The SLD algorithm simplifies the nodes updating process and messages storing process of the offset min-sum algorithm, speeding up the decoding process and reducing nearly a half of resources consumption. Besides, the SLD algorithm, introducing the semi-parallel architecture into decoding architecture, can increase the convergence rate by 2X and decrease the interconnect complexity of hardware implementation. For multi-rate QC-LDPC Codes in 802.11.n, comparing with float-point software implementation, the degradations of the fixed-point SLD algorithm with 10 iterations in FPGA are all less than 0.ldB and the throughput of different code rates are all above 100Mbps.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.