We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.
We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.
Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family
Low-density parity-check (LDPC) codes have attracted tremendous attention for their excellent error-correction performance and inherent fitness for high-parallelism implementation. With great complexity reduction and friendly for hardware implementation, the min-sum (MS) decoding algorithm for LDPC codes gains widespread applications in practical. In the MS decoding algorithm, finding the first two minima among input variable-to-check messages is the most complex part. To further reduce the complexity of the MS decoding algorithm, an efficient single-minimum (single-min) based layered MS decoding for quasi-cyclic LDPC (QC-LDPC) codes is proposed in this paper. It is found that statistically the difference between the first minimum and second minimum increases as the decoding becomes more convergent. Accordingly, in the proposed single-min scheme, the second minimum is approximately derived based on the first minimum and an index indicating the convergence degree. Besides, some other metrics that are easily obtained are used to refine the second minimum. Simulation results show that the proposed method can significantly improve the error-correction performance and lower the average number of iterations, compared with the state-of-the-art single-min based MS decoding algorithms.
The rapid evolution of 5G-NR and the increasing demand for secure and low-latency communications require strong error-correction techniques that are compatible with cryptographic systems. In this paper, a hybrid LDPC decoding algorithm, Split-Row Threshold Offset Min-Sum (SRTOMS), is proposed, which embeds the offset correction of Offset Min-Sum (OMS) within the partitioned structure of Split-Row Threshold (SRT) decoding. SRTOMS is designed for 5G-NR LDPC codes and targets a trade-off between error-correction performance and hardware complexity. Under identical conditions (BG2, rate 5/8, Z=144, AWGN channel, and six iterations), SRTOMS reaches a BER of 10−5 about 1.3 dB earlier than SRT, while remaining about 1.25 dB behind OMS, and it keeps the partitioned, low-routing structure of SRT. For three encrypted images transmitted over an AWGN channel, hardware–software co-simulation shows a sharp BER drop between 3 and 4.5 dB; at 4.5 dB, one, six and zero residual bit errors remain (BER of 1.9×10−6, 3.8×10−6 and 0), reported with 95% confidence intervals. The FPGA implementation of the SRTOMS core requires 420 LUTs and 6 DSP slices and operates with a clock period of 2.02 ns. These results indicate the potential of SRTOMS as a candidate for secure and low-complexity 5G-NR communication.
Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.
In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.
This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10−5at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$-26112bitsand1/3-8/9,respectively.ThisFPGAimplementationoftheproposedQC−LDPCdecoderdeliversapeakthroughputof13.3Gbpsandlatencyof0.77\mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.