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arXiv:2208.13022 · IEEE Transactions on Communications

Parity-Check Matrix Partitioning for Efficient Layered Decoding of QC-LDPC Codes

Teng Lu, Xuan He, Peng Kang, Jiongyue Xing, Xiaohu Tang

Published Mar 24, 2023• 5 citations
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Abstract

In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.

DOI
10.1109/tcomm.2023.3261380

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Information•Nov 1, 2024•1 citation
In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.
In this paper, we propose two algorithms to partition the parity check matrices (PCMs) for the layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes, which targets to reduce the hardware complexity and computation delay. We formulate the optimization problem of PCM partitioning, and systematically propose the principle of partitioning to guarantee a block cyclic shift property for different decoding layers. After that, we develop both greedy and enumerative partitioning algorithms, aiming at minimizing the maximum column weight of each decoding layer. We further derive a tight lower bound for the minimum achievable maximum column weight, which can help to early terminate a searching process once the lower bound is achieved. Simulation results show that the proposed algorithms are generally capable of achieving the lower bound or differ by one.
Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of Eb/N0E_b/N_0Eb​/N0​ Eb/N0 until the BER of 1e−6.
The layered scheme is famous for its efficiency and high throughput structure in decoding of LDPC codes, especially the quasi-cyclic LDPC codes, whose parity check matrices are made of cyclically-shifted identity matrices, which can be used as natural partitions of decoding layers. However, for many QC-LDPC codes, it leads to serious routing congestion if the cyclically shifted identity matrix size is taken directly as the layer partition and parallel factor in decoding. In this paper, a parity-check matrix reordering method is introduced, which can lower the decoding parallelism while keeping the layered decoding structure at the same time. The LDPC codes in DVB-S2/T2 standards are taken as an example to illustrate the proposed method, simulation and FPGA implementation shows that the method is effective in reducing the total decoder cost.
Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.