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IEEE Globecom Workshops (GC Wkshps)

Parity Check Matrix Partitioning for Layered Decoding of QC-LDPC Codes

Teng Lu, Xuan He, Peng Kang, Xiaohu Tang

Published Dec 1, 2021• 1 citation
Publisher

Abstract

In this paper, we propose two algorithms to partition the parity check matrices (PCMs) for the layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes, which targets to reduce the hardware complexity and computation delay. We formulate the optimization problem of PCM partitioning, and systematically propose the principle of partitioning to guarantee a block cyclic shift property for different decoding layers. After that, we develop both greedy and enumerative partitioning algorithms, aiming at minimizing the maximum column weight of each decoding layer. We further derive a tight lower bound for the minimum achievable maximum column weight, which can help to early terminate a searching process once the lower bound is achieved. Simulation results show that the proposed algorithms are generally capable of achieving the lower bound or differ by one.

DOI
10.1109/gcwkshps52748.2021.9682155

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Parity-Check Matrix Partitioning for Efficient Layered Decoding of QC-LDPC Codes

Teng Lu, Xuan He, Peng Kang +2 more

In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.

arXiv:2208.13022•IEEE Transactions on Communications•Mar 24, 2023•5 citations

A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

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Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.

•Sep 8, 2020•1 citation

Reduced complexity implementation of quasi-cyclic LDPC decoders by parity-check matrix reordering

Jianing Su, Zhenghao Lu

The layered scheme is famous for its efficiency and high throughput structure in decoding of LDPC codes, especially the quasi-cyclic LDPC codes, whose parity check matrices are made of cyclically-shifted identity matrices, which can be used as natural partitions of decoding layers. However, for many QC-LDPC codes, it leads to serious routing congestion if the cyclically shifted identity matrix size is taken directly as the layer partition and parallel factor in decoding. In this paper, a parity-check matrix reordering method is introduced, which can lower the decoding parallelism while keeping the layered decoding structure at the same time. The LDPC codes in DVB-S2/T2 standards are taken as an example to illustrate the proposed method, simulation and FPGA implementation shows that the method is effective in reducing the total decoder cost.

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Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of $$E_b/N_0$$ Eb/N0 until the BER of 1e−6.

EURASIP Journal on Wireless Communications and Networking•Oct 9, 2021•7 citations

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The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.

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A New Early Termination Strategy for QC-LDPC Codes Based on the Layered Message Passing Decoding

Zhejun Zhang, Guanghui He, Jun Ma

Low-density parity-check (LDPC) codes are one of the most popular linear block codes have ever been used in the communication system.The standard two-phase message passing decoding (TPMPD) algorithm and the layered message-passing decoding (LMPD) algorithm are widely used in LDPC decoder.However, the convergence speed of LMPD algorithm is much faster than that of TPMPD algorithm, particularly in the condition of high signal noise ratio (SNR).In this paper, we propose an early termination criterion for quasi-cyclic low-density parity-check (QC-LDPC) codes based on LMPD algorithm with fast convergence speed.The strategy is to dynamically reprocesses the uncorrected related layers while skipping the corrected ones.Simulations show that 3% reduction in terms of iteration numbers can be achieved with no performance loss compared to the traditional termination strategies, such as hard decision aided (HDA) strategy and parity check equations (PCE) strategy.Furthermore, the optimized early termination strategy achieves low complexity in hardware implementation.

Advances in intelligent systems research/Advances in Intelligent Systems Research•Jan 1, 2013•1 citation
In this paper, we propose two algorithms to partition the parity check matrices (PCMs) for the layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes, which targets to reduce the hardware complexity and computation delay. We formulate the optimization problem of PCM partitioning, and systematically propose the principle of partitioning to guarantee a block cyclic shift property for different decoding layers. After that, we develop both greedy and enumerative partitioning algorithms, aiming at minimizing the maximum column weight of each decoding layer. We further derive a tight lower bound for the minimum achievable maximum column weight, which can help to early terminate a searching process once the lower bound is achieved. Simulation results show that the proposed algorithms are generally capable of achieving the lower bound or differ by one.
In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.
Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.
The layered scheme is famous for its efficiency and high throughput structure in decoding of LDPC codes, especially the quasi-cyclic LDPC codes, whose parity check matrices are made of cyclically-shifted identity matrices, which can be used as natural partitions of decoding layers. However, for many QC-LDPC codes, it leads to serious routing congestion if the cyclically shifted identity matrix size is taken directly as the layer partition and parallel factor in decoding. In this paper, a parity-check matrix reordering method is introduced, which can lower the decoding parallelism while keeping the layered decoding structure at the same time. The LDPC codes in DVB-S2/T2 standards are taken as an example to illustrate the proposed method, simulation and FPGA implementation shows that the method is effective in reducing the total decoder cost.
Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of Eb/N0E_b/N_0Eb​/N0​ Eb/N0 until the BER of 1e−6.
The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.
Low-density parity-check (LDPC) codes are one of the most popular linear block codes have ever been used in the communication system.The standard two-phase message passing decoding (TPMPD) algorithm and the layered message-passing decoding (LMPD) algorithm are widely used in LDPC decoder.However, the convergence speed of LMPD algorithm is much faster than that of TPMPD algorithm, particularly in the condition of high signal noise ratio (SNR).In this paper, we propose an early termination criterion for quasi-cyclic low-density parity-check (QC-LDPC) codes based on LMPD algorithm with fast convergence speed.The strategy is to dynamically reprocesses the uncorrected related layers while skipping the corrected ones.Simulations show that 3% reduction in terms of iteration numbers can be achieved with no performance loss compared to the traditional termination strategies, such as hard decision aided (HDA) strategy and parity check equations (PCE) strategy.Furthermore, the optimized early termination strategy achieves low complexity in hardware implementation.