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IEEE International Symposium on Circuits and Systems proceedings

Efficient column-layered decoders for single block-row quasi-cyclic LDPC codes

Chuan Zhang, Xiaohu You, Zhongfeng Wang

Published Jun 1, 2014• 2 citations
Publisher

Abstract

The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.

DOI
10.1109/iscas.2014.6865153

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The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.
Single block-row quasi-cyclic low-density parity-check codes have been proposed for high-speed applications recently. However, no existing work has systematically addressed the decoder design issue for such kind of codes. In this brief, an efficient decoder architecture for such kinds of codes is proposed by exploring the geometry properties of the check matrix. Compared with conventional approaches, the proposed method can achieve more than 20.8% of memory reduction. Additionally, the subblock-sharing technique and the suboptimal low-latency searching method are employed to further reduce the hardware complexity.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
The decoding parallelism of quasi-cyclic low density parity check (QC-LDPC) codes, an important realization factor of LDPC codes, is limited by the block size. Joint row-column (JRC) decoding algorithm, an efficient decoding technique having low computation cost and small iteration number, also suffers from the decoding parallelism limitation in QC-LDPC application. In this paper, a novel LDPC-code construction method is presented and validated. This method constructs the row sets to eliminate the data access conflicts, and it clearly enhances the decoding parallelism while avoids any degradation of bit error rate (BER) performance.
In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ωLBon the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ωLB= 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ωLBor the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.
Channel coding is an important building block in communication systems. Low-density parity-check codes is one kind of prominent error correcting codes being considered in next generation industry standards. This paper presents a memory efficient, very high speed decoder architecture suited for quasi-cyclic low-density parity-check codes using modified Min-Sum decoding algorithm. In general, about seventy percent of message memory can be saved over conventional decoder architectures, and the decoding speed can be largely accelerated because of the highly efficient VLSI architecture. Consequently, the proposed approach facilitates the applications of LDPC codes in area/latency sensitive communication systems.