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Applied Mechanics and Materials

A Novel Quasi-Cyclic LDPC Codes Construction Method for High-Speed Parallel Decoding

Ming Ke Dong, Wang Da, Ya Dan Zheng, Shang Zhu Wu, Hai-ge Xiang

Published Aug 1, 2013• 0 citations
Publisher

Abstract

The decoding parallelism of quasi-cyclic low density parity check (QC-LDPC) codes, an important realization factor of LDPC codes, is limited by the block size. Joint row-column (JRC) decoding algorithm, an efficient decoding technique having low computation cost and small iteration number, also suffers from the decoding parallelism limitation in QC-LDPC application. In this paper, a novel LDPC-code construction method is presented and validated. This method constructs the row sets to eliminate the data access conflicts, and it clearly enhances the decoding parallelism while avoids any degradation of bit error rate (BER) performance.

DOI
10.4028/www.scientific.net/amm.347-350.3702

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The decoding parallelism of quasi-cyclic low density parity check (QC-LDPC) codes, an important realization factor of LDPC codes, is limited by the block size. Joint row-column (JRC) decoding algorithm, an efficient decoding technique having low computation cost and small iteration number, also suffers from the decoding parallelism limitation in QC-LDPC application. In this paper, a novel LDPC-code construction method is presented and validated. This method constructs the row sets to eliminate the data access conflicts, and it clearly enhances the decoding parallelism while avoids any degradation of bit error rate (BER) performance.
The joint row-column decoding algorithm for Low Density Parity Check (LDPC) codes is widely used in high-speed communications. However, the pipeline operation of the decoder may introduce memory access conflicts, which heavily deteriorates the decoding throughput. To essentially deal with the issue of memory access conflicts, we present a construction method of LDPC codes for joint row-column decoding algorithm. It can avoid routing congestion and reduce decoder pipeline delay. The LDPC codes constructed by the proposed method can greatly reduce the decoding iterations. Meanwhile, the performance of them is the same as the codes constructed by conventional Block Progressive Edge-Growth...
The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.
This paper proposes a new technique for constructing the Quasi-Cyclic low density parity check (QC-LDPC) codes based on row division method. The new codes offer more flexibility in term of girth, code rates and codeword length. In this method of code construction, the rows are used to form as the distance graph. Then they are transformed to a parity-check matrix in order to acquire the desired girth. The new QC-LDPC codes show good bit-error rate performance as compared to the renowned Mackay codes for given values of Eb/Noby 0.12 dB at BER of10-7.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
The existing construction of Quasi-Cyclic low-density parity-check (short for QC-LDPC) codes has not considered the problems of small stopping sets and small girth and small minimum code weight together, while their existences will lead to the BER performance of QC-LDPC codes to be much poorer than that of randomly constructed LDPC codes even decoding failure. To solve the problem, some theorems of the QC-LDPC codes without small stopping sets and small girth were proposed first. Then good QC-LDPC codes without small stopping sets and small girth were designed based on the row vectors of generator matrix. The small minimum code weight also can be prevented due to the new algorithm based on the row vectors of generator matrix, which is the new way to choose the shifted factors to construct the good QC-LDPC codes for the given prime. The effectiveness and the practicability of the algorithm are demonstrated by the simulation results. It is significant for us to analyze and optimize the design of LDPC codes.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.