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Telecom

SRTOMS: A Hybrid Split-Row Threshold Offset Min-Sum LDPC Decoder for Secure Low-Latency 5G-NR Communications

Bilal Mejmaa, Mohamed Htiti, Abdelaziz Lberni, Rachid Skouri, Ismail Akharraz, Abdelaziz Ahaitouf

Published Oct 9, 2026• 0 citations
Publisher

Abstract

The rapid evolution of 5G-NR and the increasing demand for secure and low-latency communications require strong error-correction techniques that are compatible with cryptographic systems. In this paper, a hybrid LDPC decoding algorithm, Split-Row Threshold Offset Min-Sum (SRTOMS), is proposed, which embeds the offset correction of Offset Min-Sum (OMS) within the partitioned structure of Split-Row Threshold (SRT) decoding. SRTOMS is designed for 5G-NR LDPC codes and targets a trade-off between error-correction performance and hardware complexity. Under identical conditions (BG2, rate 5/8, Z=144, AWGN channel, and six iterations), SRTOMS reaches a BER of 10−5 about 1.3 dB earlier than SRT, while remaining about 1.25 dB behind OMS, and it keeps the partitioned, low-routing structure of SRT. For three encrypted images transmitted over an AWGN channel, hardware–software co-simulation shows a sharp BER drop between 3 and 4.5 dB; at 4.5 dB, one, six and zero residual bit errors remain (BER of 1.9×10−6, 3.8×10−6 and 0), reported with 95% confidence intervals. The FPGA implementation of the SRTOMS core requires 420 LUTs and 6 DSP slices and operates with a clock period of 2.02 ns. These results indicate the potential of SRTOMS as a candidate for secure and low-complexity 5G-NR communication.

DOI
10.3390/telecom7050129

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The rapid evolution of 5G-NR and the increasing demand for secure and low-latency communications require strong error-correction techniques that are compatible with cryptographic systems. In this paper, a hybrid LDPC decoding algorithm, Split-Row Threshold Offset Min-Sum (SRTOMS), is proposed, which embeds the offset correction of Offset Min-Sum (OMS) within the partitioned structure of Split-Row Threshold (SRT) decoding. SRTOMS is designed for 5G-NR LDPC codes and targets a trade-off between error-correction performance and hardware complexity. Under identical conditions (BG2, rate 5/8, Z=144, AWGN channel, and six iterations), SRTOMS reaches a BER of 10−5 about 1.3 dB earlier than SRT, while remaining about 1.25 dB behind OMS, and it keeps the partitioned, low-routing structure of SRT. For three encrypted images transmitted over an AWGN channel, hardware–software co-simulation shows a sharp BER drop between 3 and 4.5 dB; at 4.5 dB, one, six and zero residual bit errors remain (BER of 1.9×10−6, 3.8×10−6 and 0), reported with 95% confidence intervals. The FPGA implementation of the SRTOMS core requires 420 LUTs and 6 DSP slices and operates with a clock period of 2.02 ns. These results indicate the potential of SRTOMS as a candidate for secure and low-complexity 5G-NR communication.
The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.
We propose two decoding algorithms for quasi-cyclic LDPC codes (QC-LDPC) and implement the more efficient one in this paper. These algorithms depend on the split row for the layered decoding method applied to the Min-Sum (MS) algorithm. We designate the first algorithm “Split-Row Layered Min-Sum” (SRLMS), and the second algorithm “Split-Row Threshold Layered Min-Sum” (SRTLMS). A threshold message passes from one partition to another in SRTLMS, minimizing the gap from the MS and achieving a binary error rate of 3 × 10−5 with Imax = 4 as the maximum number of iterations, resulting in a decrease of 0.25 dB. The simulation’s findings indicate that the SRTLMS is the most efficient variant decoding algorithm for LDPC codes, thanks to its compromise between performance and complexity. This paper presents the two invented algorithms and a comprehensive study of the co-design and implementation of the SRTLMS algorithm. We executed the implementation on a Xilinx Kintex-7 XC7K160 FPGA, achieving a maximum operating frequency of 101 MHz and a throughput of 606 Mbps.
Abstract This paper proposes a resource-efficient Adaptive Offset Min-Sum (A-OMS) LDPC decoder for 5G-NR Base Graph 2 (BG2) codes. A Genetic Algorithm (GA) is employed to optimize the offset factor within the check-node update, addressing the difficulty of selecting a globally optimal offset for the irregular BG2 structure. The GA operates as a meta-heuristic optimizer that minimizes the bit-error rate (BER) over a wide range of signal-to-noise ratios (SNRs). Simulation results show that the proposed GA-optimized A-OMS decoder achieves performance within 0.2–0.4 dB of belief-propagation decoding, while providing coding gains of 0.3–0.6 dB and up to a 4.6× BER reduction compared with conventional fixed-offset OMS. These improvements are obtained with approximately 35% of the computational complexity of BP decoding. The proposed approach offers a practical balance between performance and implementation efficiency for next-generation 5G-NR receivers.
This article proposes a simplified offset min-sum (SOMS) decoding algorithm for the QC-LDPC codes. It is an implementation-friendly algorithm based on a new logarithmic-likelihood-ratio (LLR) grouping technique that alleviates the computational complexity of the QC-LDPC channel-decoder. This work also presents a parallel and hardware-efficient architecture of the QC-LDPC decoder based on the suggested SOMS algorithm. Additional architectural transformations have been carried out to reduce the routing complexity of the proposed decoder and deliver lower latency and higher throughput. Comprehensive performance analysis of the SOMS algorithm has been presented under various scenarios based on the specifications of the 5G-NR standard. It shows that the suggested SOMS algorithm delivers an adequate FER of 10−5^{-5}−5at SNR of 1.3 dB while decoding 16-QAM modulated QC-LDPC code with the code rate of 1/3 and the code length of 26112 bits. Subsequently, our QC-LDPC decoder has been hardware-implemented on the FPGA platform (Xilinx Zynq-Ultrascale+ board) that operates at the maximum clock frequency of 128.36 MHz. It can be reconfigured to support seven different 5G-NR code lengths and code rates that range between 10368$-26112bitsand1/326112 bits and 1/326112bitsand1/3-8/9,respectively.ThisFPGAimplementationoftheproposedQC−LDPCdecoderdeliversapeakthroughputof13.3Gbpsandlatencyof0.778/9, respectively. This FPGA implementation of the proposed QC-LDPC decoder delivers a peak throughput of 13.3 Gbps and latency of 0.778/9,respectively.ThisFPGAimplementationoftheproposedQC−LDPCdecoderdeliversapeakthroughputof13.3Gbpsandlatencyof0.77\mu$s while decoding with 10 iterations. On comparing this work with the reported implementations, the proposed decoder has shown 7.5× higher throughput and 34% better hardware efficiency than the state-of-the-art implementations.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
This paper presents an Improved Offset Min-Sum (IOMS) algorithm for Low-Density Parity-Check (LDPC) decoders, used in 5thgeneration (5G) mobile communication. The proposed algorithm IOMS applies a multiplication factor to check-node update information messages. The simulation results show that the proposed IOMS algorithm offers a better error correction performance than the existing Min-Sum-based algorithms at the expense of a slight increase in complexity. At the BER of 10–5, the IOMS achieves a decoding gain of 0.1dB with respect to the OMS algorithm.