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Computers

An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz, Abdelaziz Ahaitouf

Published Aug 14, 2024• 11 citations
Publisher

Abstract

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

DOI
10.3390/computers13080195

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This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.
This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.
This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10−610 -^{6}10−6 between 2 to 4 dB of bit-energy to noise-power-spectral-density (Eb/N0)(\mathrm{E}_{b}/ \mathrm{N}_{0})(Eb​/N0​) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).
This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10 −2 , the decoder outperforms reference shorter codes (K40, K64) with an E b /N o gain of up to 0.9 dB.
This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10−2, the decoder outperforms reference shorter codes (K40, K64) with an Eb/No gain of up to 0.9 dB.
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W.