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Performance Simulation of a Layered QC-LDPC Decoder for URLLC Applications

Bilal Mejmaa, Chakir Aqil, Ismail Akharraz, Abdelaziz Ahaitouf

Published Jul 1, 2026• 0 citations
Publisher

Abstract

This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10−2, the decoder outperforms reference shorter codes (K40, K64) with an Eb/No gain of up to 0.9 dB.

DOI
10.1051/epjconf/202637403004/pdf

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This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10−2, the decoder outperforms reference shorter codes (K40, K64) with an Eb/No gain of up to 0.9 dB.
This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10 −2 , the decoder outperforms reference shorter codes (K40, K64) with an E b /N o gain of up to 0.9 dB.
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
Abstract Meeting the latency and reliability requirements of 5G Ultra-Reliable Low-Latency Communications (URLLC) is enabled through the adoption of short-block Low-Density Parity-Check (LDPC) codes. Traditional decoding of short-block LDPC using Belief Propagation (BP) may fail due to trapping sets, resulting in degraded decoding performance. This paper proposes a three-stage decoding algorithm that combines low-iteration BP decoding, a perturbation-based rescue process, and Maximum Likelihood (ML) based candidate validation to improve decoding reliability. When the low-iteration BP decoding stage fails to converge, the rescue stage perturbs the least reliable bits to generate multiple decoding candidates, which are subsequently evaluated using an ML-based metric to select the most likely candidate and reduce miscorrections. The proposed algorithm was evaluated through MATLAB simulations with a short-block LDPC configuration for 5G URLLC systems. QAM modulation was used and two channel models were considered, Additive White Gaussian Noise and flat Rayleigh fading. The performance was investigated for different numbers of perturbed bits and different coding rates. The results show improved decoding performance compared to standard LDPC, achieving coding gains exceeding 1 dB at low bit error rates while reducing decoding failures caused by trapping sets.
Low-density parity-check (LDPC) codes are channel code of fifth-generation(5G) New Radio(NR), and it is important to explore low-complexity decoding algorithms that are easy to implement on hardware. In order to realize 5G ultra-reliable low latency communication (URLLC), low-complexity decoding of short packets is necessary. For quasi-cyclic LDPC (QC-LDPC) codes in 5G NR, the layer offset min-sum (LOMS) algorithm and the layer normalized min-sum (LNMS) algorithm are two efficient algorithms with low complexity. The performance of these two simplified decoding algorithms is significantly affected by the values of the above two decoding parameters. In this paper, the 3D extrinsic information transfer (EXIT) chart is introduced as an analysis tool to indicate the performance of different values for the offset and normalization parameters. The simulation results show that with different values of the above two factors, the changing of the output information of EXIT chart is consistent with that of the block error rate (BLER) in decoding simulations. In addition, it is shown that this analysis method can be extended to the decoding with fixed-point inputs.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.