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International Symposium on Medical Information and Communication Technology

An decoding parameter optimization method for LDPC codes in 5G NR based on 3D EXIT chart

Wenyi Cheng, Chao Dong, Kai Niu, Zhengzhen Zhang

Published Apr 14, 2021• 2 citations
Publisher

Abstract

Low-density parity-check (LDPC) codes are channel code of fifth-generation(5G) New Radio(NR), and it is important to explore low-complexity decoding algorithms that are easy to implement on hardware. In order to realize 5G ultra-reliable low latency communication (URLLC), low-complexity decoding of short packets is necessary. For quasi-cyclic LDPC (QC-LDPC) codes in 5G NR, the layer offset min-sum (LOMS) algorithm and the layer normalized min-sum (LNMS) algorithm are two efficient algorithms with low complexity. The performance of these two simplified decoding algorithms is significantly affected by the values of the above two decoding parameters. In this paper, the 3D extrinsic information transfer (EXIT) chart is introduced as an analysis tool to indicate the performance of different values for the offset and normalization parameters. The simulation results show that with different values of the above two factors, the changing of the output information of EXIT chart is consistent with that of the block error rate (BLER) in decoding simulations. In addition, it is shown that this analysis method can be extended to the decoding with fixed-point inputs.

DOI
10.1109/ismict51748.2021.9434901

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Low-density parity-check (LDPC) codes are channel code of fifth-generation(5G) New Radio(NR), and it is important to explore low-complexity decoding algorithms that are easy to implement on hardware. In order to realize 5G ultra-reliable low latency communication (URLLC), low-complexity decoding of short packets is necessary. For quasi-cyclic LDPC (QC-LDPC) codes in 5G NR, the layer offset min-sum (LOMS) algorithm and the layer normalized min-sum (LNMS) algorithm are two efficient algorithms with low complexity. The performance of these two simplified decoding algorithms is significantly affected by the values of the above two decoding parameters. In this paper, the 3D extrinsic information transfer (EXIT) chart is introduced as an analysis tool to indicate the performance of different values for the offset and normalization parameters. The simulation results show that with different values of the above two factors, the changing of the output information of EXIT chart is consistent with that of the block error rate (BLER) in decoding simulations. In addition, it is shown that this analysis method can be extended to the decoding with fixed-point inputs.
The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.
This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10 −2 , the decoder outperforms reference shorter codes (K40, K64) with an E b /N o gain of up to 0.9 dB.
This research investigates the simulation performance of a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G New-Radio (NR) standards. The proposed work focuses on short block-length QC-LDPC codes (280,176) to meet the dual challenge of achieving ultra-low latency (<1ms) while maintaining high reliability. LDPC codes have traditionally excelled at longer code lengths; this study demonstrates the effectiveness of LDPC codes in short-length contexts through architectural optimization utilizing a layered decoding approach, which provides improved convergence speed and reduced latency compared to traditional flooding techniques. The baseline QC-LDPC decoder performs better in terms of Bit Error Rate (BER) and Block Error Rate (BLER) with only 7 iterations. For a target BLER of 10−2, the decoder outperforms reference shorter codes (K40, K64) with an Eb/No gain of up to 0.9 dB.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
With the development of low orbit satellite communication technology, how to improve the communication speed of satellite communication systems and reduce the complexity of system design has become an important research issue. Since the invention of LDPC codes, their excellent decoding performance has been favored by researchers. QC-LDPC codes have become the channel coding scheme for the fifth generation new radio (5G NR) data channel, but at the same time, it has also brought challenges to hardware design. We propose the Layered Normalized Offset Minsum and three layer static scheduling (LNOMS-SS) algorithm. On the basis of the traditional Layered Normalized Minsum algorithm (LNMS) and Layered Offset Minsum algorithm (LOMS), the update order of each layer during hierarchical decoding is determined based on the row weight, column weight, and the number of perforated non-zero elements in the BG matrix. We also implemented the algorithm in hardware and designed an 8-levels LDPC decoder. We proposed innovative designs such as a pre-processing based routing network, a segment approximation based Minsum calculation module, and an improved checksum module. The simulation and implementation results show that our proposed LNOMS-SS algorithm has stronger performance than other algorithms, with lower hardware resource consumption and decoding latency.