Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Electronics

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Tram Thi Bao Nguyen, Tuy Tan Nguyen, Hanho Lee

Published Feb 22, 2021• 41 citations
Publisher

Abstract

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

DOI
10.3390/electronics10040516

Related papers

An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz +1 more

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

Computers•Aug 14, 2024•11 citations

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio

Anuj Verma, Rahul Shrestha

This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of $10 -^{6}$ between 2 to 4 dB of bit-energy to noise-power-spectral-density $(\mathrm{E}_{b}/ \mathrm{N}_{0})$ with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

International Conference on VLSI Design•Jan 1, 2020•19 citations

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Vladimir L. Petrović, Milos M. Markovic, Dragomir El Mezeni +2 more

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%-109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

IEEE Transactions on Circuits and Systems I Regular Papers•Aug 27, 2020•67 citations

High-Performance and Low-Complexity Decoding Algorithms for 5G Low-Density Parity-Check Codes

Bich Ngoc Tran-Thi, Truong Nguyen, Trang Hoang

The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.

Journal of Communications•Jan 1, 2022•3 citations

High Throughput Priority-Based Layered QC-LDPC Decoder with Double Update Queues for Mitigating Pipeline Conflicts

Yunfeng Li, Yingchun Li, Nan Ye +3 more

A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.

Sensors•May 5, 2022•11 citations

A Comparative Study on High Performance of LDPC Decoders for 5G Applications

Y. Sugandhi Naidu, P. Vijaya Lakshmi

5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.

Journal of Engineering Science and Technology Review•Jun 1, 2026•0 citations
This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.
This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10−610 -^{6}10−6 between 2 to 4 dB of bit-energy to noise-power-spectral-density (Eb/N0)(\mathrm{E}_{b}/ \mathrm{N}_{0})(Eb​/N0​) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).
Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%-109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.
The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.
A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.