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arXiv:1204.2577 · IET Communications

Reduced-complexity column-layered decoding and implementation for LDPC codes

Z. Cui, Zhirui Wang Zhirui Wang, Xiaofang Zhang

Published Oct 14, 2011• 40 citations
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Abstract

Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.

DOI
10.1049/iet-com.2010.1002

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Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.
In this paper, we propose an extended layered decoding approach for low density parity check (LDPC) codes. Compared to conventional layered decoding algorithms, the proposed approach has no constraint in the column weight of each layer. Hence, it enables more flexibility in high-throughput LDPC decoder design with layered decoding. Simulations on structured and random LDPC codes show that the proposed decoding method achieves significantly faster convergence and slightly better error correction performance than the conventional two phase massage passing sum-product algorithm. We also propose an efficient highly parallel decoder architecture for generic quasi-cyclic LDPC codes to facilitate the practical application of the proposed decoding scheme.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
Low-density parity-check (LDPC) codes have attracted tremendous attention for their excellent error-correction performance and inherent fitness for high-parallelism implementation. With great complexity reduction and friendly for hardware implementation, the min-sum (MS) decoding algorithm for LDPC codes gains widespread applications in practical. In the MS decoding algorithm, finding the first two minima among input variable-to-check messages is the most complex part. To further reduce the complexity of the MS decoding algorithm, an efficient single-minimum (single-min) based layered MS decoding for quasi-cyclic LDPC (QC-LDPC) codes is proposed in this paper. It is found that statistically the difference between the first minimum and second minimum increases as the decoding becomes more convergent. Accordingly, in the proposed single-min scheme, the second minimum is approximately derived based on the first minimum and an index indicating the convergence degree. Besides, some other metrics that are easily obtained are used to refine the second minimum. Simulation results show that the proposed method can significantly improve the error-correction performance and lower the average number of iterations, compared with the state-of-the-art single-min based MS decoding algorithms.
We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations