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IEEE Access

Low-Complexity Architecture for High-Speed 50G-PON LDPC Decoder

Kon‐Woo Kwon, Kwang-Ok Kim, Kyeong-Hwan Doo, Hwan Seok Chung, Jeong Woo Lee

Published Jan 1, 2025• 6 citations
Publisher

Abstract

We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.

DOI
10.1109/access.2025.3540450

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We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.
We propose an enhanced phased decoding scheme and the corresponding hardware architecture based on persistent S-min candidate tracking for high-rate low-density parity-check (LDPC) codes of 50G passive optical networks (50G-PON). Conventional phased decoding provides an efficient hardware architecture but cannot reuse updated compressed check-to-variable messages (CCVMs) until the next decoding iteration, resulting in slower decoding convergence. To overcome this limitation, the proposed decoder continuously maintains and updates multiple minimum-value candidates across consecutive phases, enabling newly updated reliability information to be reused without disrupting the regular phased decoding schedule. A corresponding hardware architecture is developed while preserving the fixed-structured wiring network, pipelined processing, and low-complexity characteristics of the phased decoder. The proposed decoder is evaluated through bit error rate (BER) and block error rate (BLER) simulations and implemented on an AMD Kintex UltraScale+ FPGA to assess decoding throughput and hardware resource utilization. Evaluation results show that the proposed decoder reduces the number of clock cycles required to achieve target BER and BLER, improving the throughput of a single decoder module by 21.47% at the cost of additional hardware resources compared with the conventional phased decoder. A frequency-normalized comparison with existing FPGA-based layered decoders further indicates a substantial throughput advantage even after accounting for differences in operating frequency. These results demonstrate that the proposed decoder provides an effective hardware solution for latency-sensitive high-speed 50G-PON receivers.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.
This paper presents a low complexity, very high speed decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes, specifically Euclidian geometry (EG) based QC-LDPC codes. Algorithmic transformation and architectural level optimizations are employed to increase the clock speed. Enhanced partially parallel decoding architectures are proposed to linearly increase the overall throughput with the introduction of a small percentage of extra hardware. Based on the proposed architecture, a FPGA implementation of a (8176, 7154) EG-LDPC decoder can achieve a worst-case throughput of 169 Mbit/s.
In this paper, we present a cost-efficient low-density parity-check (LDPC) decoder architecture tailored to meet the high throughput demands of 50G passive optical network (PON) systems. Building upon a previous layered decoder architecture, the complex multiplexing networks are specifically optimized for the PON LDPC codes, facilitating partially-parallel processing while minimizing congestion overheads. By incorporating advanced low-cost optimization schemes, the prototype PON LDPC decoder achieves a decoding throughput of 2.94 Gb/s, surpassing state-of-the-art approaches by 2.38-fold.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.