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IEEE International Symposium on Circuits and Systems proceedings

Low Complexity, High Speed Decoder Architecture for Quasi-Cyclic LDPC Codes

Zhongfeng Wang, Qingwei Jia

Published Jul 27, 2005• 26 citations
Publisher

Abstract

This paper presents a low complexity, very high speed decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes, specifically Euclidian geometry (EG) based QC-LDPC codes. Algorithmic transformation and architectural level optimizations are employed to increase the clock speed. Enhanced partially parallel decoding architectures are proposed to linearly increase the overall throughput with the introduction of a small percentage of extra hardware. Based on the proposed architecture, a FPGA implementation of a (8176, 7154) EG-LDPC decoder can achieve a worst-case throughput of 169 Mbit/s.

DOI
10.1109/iscas.2005.1465953

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This paper presents a low complexity, very high speed decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes, specifically Euclidian geometry (EG) based QC-LDPC codes. Algorithmic transformation and architectural level optimizations are employed to increase the clock speed. Enhanced partially parallel decoding architectures are proposed to linearly increase the overall throughput with the introduction of a small percentage of extra hardware. Based on the proposed architecture, a FPGA implementation of a (8176, 7154) EG-LDPC decoder can achieve a worst-case throughput of 169 Mbit/s.
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In this paper, an area efficient partially parallel decoder architecture suited for (modified) min-sum decoding algorithm for general high rate quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. To reduce the hardware complexity for parallel processing, an efficient data scheduling unit is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Typically, over 30% of memory can be saved with the architecture presented in this paper. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
In this paper, a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check codes using (modified) min-sum decoding algorithm is proposed. In general, more than thirty percent of memory can be saved over conventional partially parallel decoder architectures. To reduce the computation delay of check-node processing unit, an efficient architecture based on variants of rank order filter is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems
We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.
Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm5) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out.