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International SoC Design Conference

Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON Standard

Jeongwon Choe, Youngjoo Lee

Published Aug 19, 2024• 1 citation
Publisher

Abstract

In this paper, we present a cost-efficient low-density parity-check (LDPC) decoder architecture tailored to meet the high throughput demands of 50G passive optical network (PON) systems. Building upon a previous layered decoder architecture, the complex multiplexing networks are specifically optimized for the PON LDPC codes, facilitating partially-parallel processing while minimizing congestion overheads. By incorporating advanced low-cost optimization schemes, the prototype PON LDPC decoder achieves a decoding throughput of 2.94 Gb/s, surpassing state-of-the-art approaches by 2.38-fold.

DOI
10.1109/isocc62682.2024.10762337

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IEEE International Symposium on Circuits and Systems proceedings•May 1, 2007•14 citations
In this paper, we present a cost-efficient low-density parity-check (LDPC) decoder architecture tailored to meet the high throughput demands of 50G passive optical network (PON) systems. Building upon a previous layered decoder architecture, the complex multiplexing networks are specifically optimized for the PON LDPC codes, facilitating partially-parallel processing while minimizing congestion overheads. By incorporating advanced low-cost optimization schemes, the prototype PON LDPC decoder achieves a decoding throughput of 2.94 Gb/s, surpassing state-of-the-art approaches by 2.38-fold.
This Letter presents a layered ternary message passing (LTMP) decoder for the low-density parity-check (LDPC) code tailored for 50G passive optical networks (50G-PON). The proposed decoder adopts a layered architecture, and a corresponding density evolution analysis that enhances error correction performance is introduced. Additionally, we propose an optimization method for parameter combinations, which effectively achieves stronger performance. Results indicate that the LTMP decoder achieves exceptional error correction capabilities for the LDPC code in 50G-PON, even under low-precision input conditions.
We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.
We propose an enhanced phased decoding scheme and the corresponding hardware architecture based on persistent S-min candidate tracking for high-rate low-density parity-check (LDPC) codes of 50G passive optical networks (50G-PON). Conventional phased decoding provides an efficient hardware architecture but cannot reuse updated compressed check-to-variable messages (CCVMs) until the next decoding iteration, resulting in slower decoding convergence. To overcome this limitation, the proposed decoder continuously maintains and updates multiple minimum-value candidates across consecutive phases, enabling newly updated reliability information to be reused without disrupting the regular phased decoding schedule. A corresponding hardware architecture is developed while preserving the fixed-structured wiring network, pipelined processing, and low-complexity characteristics of the phased decoder. The proposed decoder is evaluated through bit error rate (BER) and block error rate (BLER) simulations and implemented on an AMD Kintex UltraScale+ FPGA to assess decoding throughput and hardware resource utilization. Evaluation results show that the proposed decoder reduces the number of clock cycles required to achieve target BER and BLER, improving the throughput of a single decoder module by 21.47% at the cost of additional hardware resources compared with the conventional phased decoder. A frequency-normalized comparison with existing FPGA-based layered decoders further indicates a substantial throughput advantage even after accounting for differences in operating frequency. These results demonstrate that the proposed decoder provides an effective hardware solution for latency-sensitive high-speed 50G-PON receivers.
Efficient error correction in high-speed communication networks, such as the 50G passive optical network (50G-PON), is paramount. This Letter focuses on optimizing a layered non-surjective finite alphabet iterative decoder (LNS-FAID) for 50G-PON, with an emphasis on high-throughput and low-power consumption. We propose using a distinct lookup table (LUT) for each iteration to enhance decoding performance and lower error floors. Additionally, we improve the 2-bit LNS-FAID architecture by adding operational states and a sign backtracking (SBT) strategy. This paper also introduces a hybrid precision model that merges 3-bit and 2-bit LNS-FAIDs, which balances error correction with computational efficiency. Our simulation results show that these approaches significantly improve the performance of the LDPC code in 50G-PON.
In this paper, a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check codes using (modified) min-sum decoding algorithm is proposed. In general, more than thirty percent of memory can be saved over conventional partially parallel decoder architectures. To reduce the computation delay of check-node processing unit, an efficient architecture based on variants of rank order filter is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.