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International Conference on Communications and Networking in China (ChinaCom)

New and efficient decoding architecture for Quasi-Cyclic LDPC codes

Zhiming Fan, Zhanji Wu, Hui Che, Xiaoping Zhou

Published Aug 1, 2014• 0 citations
Publisher

Abstract

In this paper, a new and efficient decoding architecture, Single-Scan Layer Decoding (SLD), is realized in FPGA for multi-rate Quasi-Cyclic LDPC (QC-LDPC) codes. The SLD algorithm simplifies the nodes updating process and messages storing process of the offset min-sum algorithm, speeding up the decoding process and reducing nearly a half of resources consumption. Besides, the SLD algorithm, introducing the semi-parallel architecture into decoding architecture, can increase the convergence rate by 2X and decrease the interconnect complexity of hardware implementation. For multi-rate QC-LDPC Codes in 802.11.n, comparing with float-point software implementation, the degradations of the fixed-point SLD algorithm with 10 iterations in FPGA are all less than 0.ldB and the throughput of different code rates are all above 100Mbps.

DOI
10.1109/chinacom.2014.7054294

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In this paper, a new and efficient decoding architecture, Single-Scan Layer Decoding (SLD), is realized in FPGA for multi-rate Quasi-Cyclic LDPC (QC-LDPC) codes. The SLD algorithm simplifies the nodes updating process and messages storing process of the offset min-sum algorithm, speeding up the decoding process and reducing nearly a half of resources consumption. Besides, the SLD algorithm, introducing the semi-parallel architecture into decoding architecture, can increase the convergence rate by 2X and decrease the interconnect complexity of hardware implementation. For multi-rate QC-LDPC Codes in 802.11.n, comparing with float-point software implementation, the degradations of the fixed-point SLD algorithm with 10 iterations in FPGA are all less than 0.ldB and the throughput of different code rates are all above 100Mbps.
This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software.The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates,lengths and parity-check matrix structures,and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies.Some complicated message update is implemented by a hardware accelerator,thus the decoding throughput is improved.According to the quasi-cyclic structure of the parity-check matrix,the messages are stored and processed by blocks in decoding.Parallel message processing can also be realized with a small increase in implementation complexity.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
A multi-rate decoder of Quasi-Cyclic LDPC(QC-LDPC) decoder is presented based on the improvement of layered decoding algorithm.The implementation has larger bit throughput resulting from fast convergence speed by more than 50 percent in terms of decoding iterations.Only four memories are used to store the messages which significantly reduce the area and the power dissipation.Adjusted integer quantization of layered decoding algorithm for check-node updating reduces the complexity and the correction factor guarantees the error rate performance.The proposed decoding architecture is implemented in the standard recommended.The decoder consumes 0.6 million gates,and reaches a throughput of 134 Mb/s at a clock frequency of 110 MHz with rate of 1/2.
The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as simplified code representations in the encoder and decoder. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. The decoder uses check node merging to increase the convergence speed of the algorithm. Check node merging allows the decoder to achieve the same performance with a significantly lower number of iterations, thereby increasing the throughput. The feasibility of a check node merging decoder is investigated for codes from IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the check node merging algorithm allows the decoder to be implemented using lower parallelization factors, thereby reducing the logic complexity. The designs have been synthesized to an Altera Cyclone II FPGA, and results show significant increases in throughput at high SNR.
Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.