The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic (4JL) gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance mi). We have developed a speedup method in which an inductance is connected to Ri in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. 40 % speedup of the gate switching was demonstrated by a logic delay experiment using submicron NbN/MgO/NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.