Logic gates using stacked Josephson junctions

Yuriy Makhlin, Gerd Schön, Alexander Shnirman

Yuriy Makhlin, Gerd Schön, Alexander Shnirman

Quentin Herr, Trent Josephsen, Anna Herr

Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.

Hideyuki Nagaishi, Kouji Nakahara, H. Hasegawa +1 more

Abstract DC‐powered Josephson logic gates have the advan tage of being free from operation error due to crosstalk from power current in contrast to ordinary ac‐powered Josephson logic gates. One of these, the HUFFLE (hybrid unlatching flip‐flop logic element) gate using stacked Josephson interferometers (JI) can execute complicated logic functions by itself. Therefore, high‐Speed operation of logic circuits using HUFFLE gates may be expected because the number of logic stages in the circuits is reduced. to investigate the improvement in circuit per formance by using HUFFLE gates with the stacked structure, the authors have fabricated a 6‐bit arithmetic logic unit (ALU) and tested its operation. Two new logic gales, exclusive OR and majority, newly developed using the stacked structure have been developed. the ALU which performs the four functions, AND, OR, exclusive OR, and ADD, is realized with seven logic stages. Ac cordingly, reduction in the number of logic stages and execution time of the ALU by use of the stacked HUF FLE gate family is confirmed.

S. Takada, S. Kosaka, H. Hayakawa

Yu. M. Shukrinov, I. R. Rahmonov, Andrej Plecenik +4 more

Two parallel stacks of coupled Josephson junctions are investigated to clarify the physics of transitions between the rotating and oscillating states and their effect on the IV-characteristics of the system. The detailed study of phase dynamics and bias dependence of the superconducting and diffusion currents allows one to explain all features of simulated IV-characteristics and demonstrate the correspondence in their behavior. The coupling between JJ in the stacks leads to the branching of IV-characteristics and a decrease in the hysteretic region. The crucial role of the diffusion current in the formation of the IV-characteristic of the parallel stacks of coupled Josephson junctions is demonstrated. We discuss the effect of symmetry in a number of junctions in the stacks and show a decrease of the branching in the symmetrical stacks. The observed effects might be useful for development of superconducting electronic devices based on intrinsic Josephson junctions.