Reversible Fluxon Logic for Future Computing
Kevin D. Osborn, Waltraut Wustmann
Today's industrial digital logic gates are reaching a technological limit and meanwhile, superconducting circuits produce fundamentally different technologies for the future of digital computing. The standard logic is irreversible and yet superconducting circuits allow digital reversible logic with a much higher energy efficiency per gate operation. Previous reversible gate circuits were “adiabatic,” meaning that they used adiabatic-clocking waveforms for their operation power. However, we are studying logic starting from a ballistic model, where ftuxons enable gates using only energy from their inertia. Our ftuxons are defined in Long Josephson Junctions (LJJs) and may travel ballistically, similar to a particle with negligible damping. Once a ftuxon's energy approaches close enough to the gate, a resonance is induced at the gate and the ftuxon loses its definite topology. Gates are comprised of the (few Josephson-penetration-depth long) ends of LJJs and a connecting circuit interface. Only after the resonance does a ftuxon get formed and yield the gate result without external power: a ftuxon for bit-state 0 or an antiftuxon for bit-state 1. Through earlier analysis of the numerically discovered phenomena we find that dynamics can be described with ftuxon- and antiftuxon-like excitations at the ends of LJJs within the gate. The bit-switching action in our gates is resonant indicating fundamentally different dynamics than the classic model of adiabatic reversible circuits. Our ballistic Reversible Fluxon Logic (RFL) gates have no added damping and calculated energy efficiencies of over 97%. Thus in our dynamical process the “bit energy” is preserved. However, irreversible logic completely dissipates this at each operation (e.g., charging energy in CMOS or SFQ energy in irreversible SFQ logic). An RFL gate can achieve a fast gate operation since its resonance is only few JJ plasma periods. We also describe the CNOT in our technology. It is enabled by a couple of vital gates: A IDSN logic gate, similar to our other ballistic gates, and a Store-aNd-Launch (SNL) timing gate to ensure proper synchronization of the bits. The latter allows bit storage followed by launching of a data ftuxon using an adiabatic pulse from a clock ftuxon with lower energy than the data ftuxon for good CNOT efficiency.
IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2019•4 citations