Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Journal of Physics Conference Series

An RSFQ flexible-precision multiplier utilizing bit-level processing

Nobutaka Kito, Kazuyoshi Takagi

Published Jul 1, 2021• 1 citation
Publisher

Abstract

Abstract An RSFQ flexible-precision multiplier is proposed. The circuit can perform multiplication with specified bit-width within a predefined bit range. The calculation bit-width can be changed in every operation. When the bit-width of a calculation decreases, the latency in cycles is reduced. The proposed circuit calculates the multiplication result with bit-level processing to save the circuit area. The circuit carries out multiplication by counting pulses on a signal line. An RSFQ flexible-precision matrix multiplication circuit based on the proposed multiplier is also proposed. Its internal multipliers share many component circuits and it is implemented in a compact area.

DOI
10.1088/1742-6596/1975/1/012025

Related papers

Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing

Nobutaka Kito, Ryota ODAKA, Kazuyoshi Takagi

A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.

IEICE Transactions on Electronics•Jun 30, 2019•4 citations

Design of 8-Bit RSFQ Based Multiplier for DSP Application

N. Kamakshamma, P. Kullaya Swamy

Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.

International Journal of Innovative Research in Electronics and Communications•Jan 1, 2015•0 citations

32-Bit 4 × 4 Bit-Slice RSFQ Matrix Multiplier

Guang-Ming Tang, Pei-Yao Qu, Xiaochun Ye +2 more

A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.

IEEE Transactions on Applied Superconductivity•May 18, 2018•8 citations

A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8×8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm21.0-μm fabrication technology. The simulation result shows correct operation at 62.5 GHz.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2015•2 citations

RSFQ Parallel Multiplier

Irina Kataeva, Henrik Engseth, E. Tolkacheva +1 more

This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.

•Jan 1, 2003•1 citation

32 × 32-Bit 4-Bit Bit-Slice Integer Multiplier for RSFQ Microprocessors

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.

IEEE Transactions on Applied Superconductivity•Feb 1, 2017•15 citations
Abstract An RSFQ flexible-precision multiplier is proposed. The circuit can perform multiplication with specified bit-width within a predefined bit range. The calculation bit-width can be changed in every operation. When the bit-width of a calculation decreases, the latency in cycles is reduced. The proposed circuit calculates the multiplication result with bit-level processing to save the circuit area. The circuit carries out multiplication by counting pulses on a signal line. An RSFQ flexible-precision matrix multiplication circuit based on the proposed multiplier is also proposed. Its internal multipliers share many component circuits and it is implemented in a compact area.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8×8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm21.0-μm fabrication technology. The simulation result shows correct operation at 62.5 GHz.
This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.
A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.