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RSFQ Parallel Multiplier

Irina Kataeva, Henrik Engseth, E. Tolkacheva, Anna Kidiyarova-Shevchenko

Published Jan 1, 2003• 1 citation
OpenAlex

Abstract

This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.

Related papers

Superconductor Digital Signal Processor

Irina Kataeva

Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.

•Jan 1, 2007•0 citations

RSFQ 4-bit Bit-Slice Integer Multiplier

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz.

IEICE Transactions on Electronics•Jan 1, 2016•12 citations

RSQO asynchronous serial multiplier and spreading codes generator for multiuser detector

Anna Kidiyarova-Shevchenko, K. Yu. Platov, E. Tolkacheva +1 more

Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.

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Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.

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Stanislav V. Polonsky, J.C. Lin, Alexander V. Rylyakov

We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>

IEEE Transactions on Applied Superconductivity•Jun 1, 1995•28 citations

Design and low speed testing of a four-bit RSFQ multiplier-accumulator

Quentin Herr, Nada Vukovic, C.A. Mancini +7 more

We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•24 citations
This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRWs 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.
Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.
A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz.
Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.
A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlOx/Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109multiplications per second.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.